In-Depth Study of Xilinx High-Speed Transceivers Serdes

In-Depth Study of Xilinx High-Speed Transceivers SerdesIn-Depth Study of Xilinx High-Speed Transceivers Serdes

1. Why Use Serdes

In-Depth Study of Xilinx High-Speed Transceivers SerdesIn-Depth Study of Xilinx High-Speed Transceivers Serdes

　　

Traditional source-synchronous transmission separates clock and data. There are no issues at lower rates (<1000M).

In-Depth Study of Xilinx High-Speed Transceivers Serdes

As the rates increase, this becomes problematic

In-Depth Study of Xilinx High-Speed Transceivers Serdes

　　Due to inconsistent delay and jitter in transmission lines, the receiver cannot sample data correctly, resulting in misaligned eye diagrams. This leads to the idea of recovering the clock from the data for sampling, known as CDR. In-Depth Study of Xilinx High-Speed Transceivers Serdes　　This eliminates the issue of inconsistent delays, and slight jitter will not affect sampling (the recovered clock will jitter with the data).In-Depth Study of Xilinx High-Speed Transceivers SerdesIn-Depth Study of Xilinx High-Speed Transceivers Serdes

2. Why Use 8b10b and 64b66b?

In-Depth Study of Xilinx High-Speed Transceivers SerdesIn-Depth Study of Xilinx High-Speed Transceivers SerdesIn-Depth Study of Xilinx High-Speed Transceivers Serdes

1. Provides Sufficient Transitions to Recover the Clock

In-Depth Study of Xilinx High-Speed Transceivers Serdes

　　However, there is a problem; both ends of the transceiver must share a ground, which is often difficult to achieve.

In-Depth Study of Xilinx High-Speed Transceivers Serdes

　　Thus, differential signal sampling is used to prevent common-mode voltage from causing excessive current at the receiver end, employing a current-driven mode. The receiver has a capacitor for AC coupling to block DC. This introduces another issue, the need for DC balance. Therefore, we have another reason below.In-Depth Study of Xilinx High-Speed Transceivers Serdes

2. DC Balance, i.e., Equal Number of 0s and 1s.

In-Depth Study of Xilinx High-Speed Transceivers SerdesIn-Depth Study of Xilinx High-Speed Transceivers Serdes

3. Run Length, Maximum Length of Consecutive 0s and 1s

　　AGC (Automatic Gain Control) requires AC components to achieve amplification.

In-Depth Study of Xilinx High-Speed Transceivers Serdes　　In-Depth Study of Xilinx High-Speed Transceivers Serdes

4. Comma Code, K Code

In high-speed serial streams on Serdes, the receiver needs to re-serialize and convert them into parallel multiple words. How do we find the word boundaries for alignment? This requires a special sequence, known as the comma code. Some control needed during transmission should preferably not conflict with the data, which is the K code. Based on these four reasons, the 8b10b and 64b66b encoding schemes were developed.In-Depth Study of Xilinx High-Speed Transceivers SerdesIn-Depth Study of Xilinx High-Speed Transceivers Serdes

3. 8b10b Encoding

In-Depth Study of Xilinx High-Speed Transceivers SerdesIn-Depth Study of Xilinx High-Speed Transceivers Serdes

　In summary, 8b10b encoding transforms 8-bit data into 10-bit data, ensuring that the number of 1s or 0s does not exceed 6, and the number of consecutive 1s or 0s does not exceed 4. This significantly reduces the original 1024 Hamming space encoding. It contains 256 data codes and 12 control codes, ensuring that data and control codes do not overlap.

In-Depth Study of Xilinx High-Speed Transceivers Serdes　　K28.1, K28.5, and K28.7 can serve as delimiter codes, also known as comma codes, helping the receiver find byte boundaries in the serial data stream. The commonly used K28.5 is 0xBC. Since normally transmitted data may also contain 0xBC, how can we distinguish it? A separate control line is used; tx_is_K is pulled high when transmitting K codes and pulled low when transmitting data, controlling whether the 8b10b encoding module encodes data or K control codes.In-Depth Study of Xilinx High-Speed Transceivers SerdesIn-Depth Study of Xilinx High-Speed Transceivers Serdes

4. Some Details of Xilinx Serdes

In-Depth Study of Xilinx High-Speed Transceivers SerdesIn-Depth Study of Xilinx High-Speed Transceivers SerdesIn-Depth Study of Xilinx High-Speed Transceivers Serdes

1. Usage of COMMA Code

　　K28.5, 0xBC, +0101_111100, -1010_000011; for detecting byte segmentation. Use other K codes for frame start, frame end, clock correction, and data alignment.

In-Depth Study of Xilinx High-Speed Transceivers Serdes

2. Multi-Byte Processing

When data rates are high, the external width may be 2 words (16 bits) or 4 words (32 bits). If the transmitting and receiving parties do not agree on which word to send the comma code, it can detect word boundaries, but the receiving end may experience byte-swapping issues. For any single COMMA data alignment, choose even byte alignment. When sending, 0x5ABC->2’b01.

In-Depth Study of Xilinx High-Speed Transceivers Serdes

It is also possible to send combined comma codes, which concatenate the NP commas for transmission, allowing the receiver to detect 16-bit double-word boundaries and avoid the previous issue. When sending, 0xBCBC->2’b11

In-Depth Study of Xilinx High-Speed Transceivers Serdes

Note: Do not select decode valid comma only, as other K codes may also be sent for control. In any case, 8b10b uses the resources of the transceiver hard core, which should not be wasted.

In-Depth Study of Xilinx High-Speed Transceivers Serdes

3. Loopback Settings:

1. “000”: Normal mode 2. “001”: Near-end PCS loopback 3. “010”: Near-end PMA loopback 4. “100”: Far-end PMA loopback 5. “110”: Far-end PCS loopback Note that the loopback configured in Xilinx instantiated example files refers to reserved loopback interfaces and still requires manual configuration.

In-Depth Study of Xilinx High-Speed Transceivers Serdes

4. FSM_Down State Machine

In-Depth Study of Xilinx High-Speed Transceivers Serdes

In the Monitor Data_Valid module, the correct signal from frame_check is used; a verification failure will reset GTrxreset. This feedback can be ignored, and it can be set directly to 1. Manual adjustments are needed.

Source: CSDN Blog

In-Depth Study of Xilinx High-Speed Transceivers Serdes

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In-Depth Study of Xilinx High-Speed Transceivers Serdes

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