eFPGA

Design and Implementation of SoC IP Verification Scheme Based on ZYNQ

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Design and Implementation of SoC IP Verification Scheme Based on ZYNQ

Authors:Tao Qingping, Shang Guoqing, Zhu QingAffiliation:1. China Electronics Technology Group Corporation, the 58th Research Institute, Wuxi, Jiangsu 214035.Abstract:With the popularity of SoC chip design, the demand for various IP designs is also increasing. The challenge for IC design engineers and verification engineers is how to quickly and accurately verify the correctness of these IP functions. … Read more

Detailed Explanation of Binary Operations (Addition, Subtraction, Multiplication, Division) in FPGA

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Detailed Explanation of Binary Operations (Addition, Subtraction, Multiplication, Division) in FPGA

In FPGA design, binary operations are one of the most fundamental and commonly used logical operations, with addition, subtraction, multiplication, and division widely applied in digital signal processing, control algorithms, and data computation scenarios. To simplify hardware implementation while accommodating signed operations, FPGAs typically use two’s complement representation for signed numbers. Using two’s complement not … Read more

FPGA Tutorial Case 5: ROM Design and Implementation Based on Vivado Core

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FPGA Tutorial Case 5: ROM Design and Implementation Based on Vivado Core

01ROM Design and Implementation Based on Vivado Core In FPGAs, ROM is a very important module that allows complex data to be output based on address information. Vivado is a high-level design suite from Xilinx used for the design and verification of FPGAs (Field Programmable Gate Arrays). In Vivado, we can use high-level design methods … Read more

A Step-by-Step Guide to Utilizing the MIPI Interface on iSilicon FPGAs: A Game Changer for Video Project Development!

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A Step-by-Step Guide to Utilizing the MIPI Interface on iSilicon FPGAs: A Game Changer for Video Project Development!

Hello everyone! Today, we are going to discuss a very practical topic—how to use the MIPI interface on iSilicon FPGAs. Whether it’s for camera image acquisition or display control, MIPI is a very common interface standard. Mastering it will greatly enhance your video project development efficiency! The iSilicon FPGA supports the use of the MIPI … Read more

Xilinx Common IP Core Series | Design and Implementation of a Signal Generator Based on DDS

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Xilinx Common IP Core Series | Design and Implementation of a Signal Generator Based on DDS

「Xilinx Common IP Core Series」 Design and Implementation of a Signal Generator Based on DDS (Includes Verilog Code + Simulation Waveform) In fields such as communications, radar, and test instruments, the signal generator is one of the most fundamental and important modules. Whether for system validation or algorithm experimentation, a stable and flexible waveform source … Read more

FIR Filter Series: Joint Simulation Verification Platform for FIR IP using Matlab, Vivado, and Modelsim (Part 1)

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FIR Filter Series: Joint Simulation Verification Platform for FIR IP using Matlab, Vivado, and Modelsim (Part 1)

1. Generating Input Waveforms for FIR IP in Matlab 2. Generating Filter Coefficients for FIR IP in Matlab In FPGA-based digital signal processing, data transfer and simulation verification between Matlab, Vivado, and Modelsim are required. The typical approach is for Matlab to generate input signals for the Verilog module as simulation stimuli, followed by testing … Read more

UART Asynchronous Serial Communication Circuit Design Verilog Code for Quartus FPGA_C4_V2.1 Experimental Board

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UART Asynchronous Serial Communication Circuit Design Verilog Code for Quartus FPGA_C4_V2.1 Experimental Board

Name: UART Asynchronous Serial Communication Circuit Design Verilog Code for Quartus FPGA_C4_V2.1 Experimental Board Software: Quartus Language: Verilog Code Function: Function Description Enhance the transmission rate of UART communication, supporting higher baud rates (such as 115200, 230400, or higher). Implementation Method 1. Optimize Baud Rate Division Use a higher system clock frequency (e.g., 100MHz) and … Read more

FPGA Functional Module: Photointerrupter Signal Reading

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FPGA Functional Module: Photointerrupter Signal Reading

1. Photointerrupter 1.1 Common Types of Photointerrupters (1) Slotted Photointerrupter This sensor has the emitter and detector positioned opposite each other, detecting objects that pass through the slot between the emitter and detector. There are various photoelectric sensors with different slot widths or depths depending on the detected object. (2) Reflective Photointerrupter This type of … Read more

How is the Netlist of an FPGA Generated?

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How is the Netlist of an FPGA Generated?

Have you ever encountered a situation where you want to share your code with someone else, but you only want them to use it without having access to the source code? In this case, you can provide them with the netlist file of your code.In this way, they will have usage rights but no modification … Read more

One Device for Frequency Modulation and Amplitude Modulation: FPGA DDS Waveform Generator

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One Device for Frequency Modulation and Amplitude Modulation: FPGA DDS Waveform Generator

With a single FPGA, you can control arbitrary waveform generation, including frequency modulation and amplitude modulation! This project utilizes the DDS module and high-speed DAC in the “Little Foot” FPGA development board to achieve high-quality output of various waveforms such as sine, square, and triangle waves. The control method is very intuitive: switch waveform modes … Read more