Authors:Tao Qingping, Shang Guoqing, Zhu QingAffiliation:1. China Electronics Technology Group Corporation, the 58th Research Institute, Wuxi, Jiangsu 214035.Abstract:With the popularity of SoC chip design, the demand for various IP designs is also increasing. The challenge for IC design engineers and verification engineers is how to quickly and accurately verify the correctness of these IP functions. In response to these needs, a design and implementation scheme for SoC IP verification based on ZYNQ is proposed. Starting from some traditional verification methods, the problems encountered in verification are listed, and the overall framework of the verification scheme is elaborated, along with the hardware resources and software advantages of the ZYNQ platform. It also discusses how to encapsulate the IP to be verified, integrate it into the ZYNQ system, and use the SDK to write software code to test the IP under examination. Finally, a verification example of the rdc IP is provided to illustrate the feasibility and superiority of this scheme.Introduction:
SoC is an integrated chip that has many advantages over traditional chips, including high reliability, small size, low power consumption, and high integration[1]. It is now commonly found in many smart devices, such as Huawei’s Kirin 9000 mobile processor chip and Qualcomm’s Snapdragon 888, and even some customized chips for special needs utilize SoC technology. The hardware of SoC is usually designed based on the IP model[2], so the popularity of SoC has also spawned various IP designs, especially those with standard bus protocols that can be easily embedded into SoC chips. The concept of on-chip bus[3] is quite important in SoC design. Currently, several common buses include: AXI bus[4-5], which is the most widely used and high-performance on-chip bus; AHB bus, which is the most widely used high-performance low-power bus, commonly adopted by ARM’s Cortex-M series; and APB bus, mainly used for low-bandwidth peripheral devices such as UART, SPI, etc.
As is well known, since SoC design relies on IP support, these IPs need to be verified and simulated before being integrated into the SoC. Especially for those IPs with bus interfaces, verifiers must not only understand the functionality of the IP but also be familiar with various bus protocols, which undoubtedly increases the difficulty of verification. The traditional solution is an MCU+FPGA implementation scheme or a similar FPGA prototype verification architecture[6]. This not only requires high design capabilities in hardware, such as communication between the MCU and FPGA, especially in parallel communication[7], but may also require verifiers to convert some bus protocols, such as converting XINTF to APB bus protocol or EMIF interface to APB bus protocol, which raises the technical requirements for verifiers. The prototype verification architecture also requires the implementation of a core, making it less convenient. Through the above analysis, it is found that traditional solutions generally have high requirements for both hardware and software design capabilities, and if either side has issues, debugging can be time-consuming and labor-intensive, potentially leading to hardware redesign and delaying project progress.
Source: “Electronic Technology Application” Magazine, October IssueClick belowto read the original text and download the paper PDF
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