Mr. Big Cat says: Translation compilation of Chapter 13 from the book RFSoC-Book, detailed introduction of this book can be found in the first article of this series. “An open-source masterpiece, ‘Software Defined Radio Based on Zynq UltraScale+ RFSoC’” Mr. Big Cat, WeChat public account: Mr. Big Cat’s Little Bookcase, an open-source masterpiece, ‘Software Defined … Read more
1. Introduction to FFT Algorithm and Vivado FFT IP Core 1. What is FFT? FFT (Fast Fourier Transform) is an efficient algorithm for computing the Discrete Fourier Transform (DFT). The mathematical definition of DFT is: Direct computation of DFT requires N multiplications and additions, while FFT reduces the complexity to:, significantly improving computational efficiency, making … Read more
Light Up Your First FPGA Project: A Blinking LED When you see the small light on the circuit board start to blink regularly, it means your FPGA program is truly “alive”! Below, we will guide you step by step to achieve this ceremonial introductory experiment. 1. 🔌 Hardware Preparation Connect the Development Board Insert the … Read more
Introduction Typically, after generating Vivado IP, we submit the .xci files to the version control system. However, once we change the FPGA device or upgrade the Vivado version, these IPs often cannot be directly re-added, leading to significant challenges in project compatibility and migration. If we could automatically generate IPs solely through scripts, it would … Read more
1. Explanation of Other Settings on the IP Core Configuration Implementation Page: 1️⃣ Coefficient Fractional Bits Function: Specifies the number of bits used for the fractional part of the FIR filter coefficients. Significance: Vivado quantizes floating-point coefficients (e.g., 0.125) into fixed-point integers, calculated as follows: ActualValueIntegerRepresentationIndication Example: If <span>Coefficient Width = 10</span>, <span>Coefficient Fractional Bits … Read more
01Design and Implementation of FIR Filter Based on Vivado CoreThe Finite Impulse Response (FIR) filter is a widely used filter in the field of digital signal processing, known for its good stability, ease of implementation, and linear phase characteristics. The FIR filter is a linear time-invariant system composed of a set of coefficients, which performs … Read more
01Design and Implementation of a Complex Multiplier Based on Vivado IP CoreIn the fields ofdigital signal processing and image processing, complex multiplication is often required. A complex multiplier is a core component for performing this operation. Particularly in digital signal processing, complex multiplication has numerous applications, including signal mixing, FFT, and IFFT. The complex multiplier … Read more
01ROM Design and Implementation Based on Vivado Core In FPGAs, ROM is a very important module that allows complex data to be output based on address information. Vivado is a high-level design suite from Xilinx used for the design and verification of FPGAs (Field Programmable Gate Arrays). In Vivado, we can use high-level design methods … Read more
1. Configuration of FIR IP in Vivado 2. Setting up the simulation environment with Vivado and Modelsim 1. Importing Data from Matlab to Modelsim In the previous chapter, we designed a FIR digital filter using Vivado, and in the Modelsim simulation, the output data from the FIR IP was written to the data_out.txt file. This … Read more
1. Configuration of FIR IP in Vivado 2. Setting up the simulation environment with Vivado and Modelsim 1. Configuration of FIR IP in Vivado Vivado provides FIR IP for implementing low-pass filter FIR functionality. For specific details, please refer to the corresponding official manual. Here, we will briefly introduce the configuration interface of the FIR … Read more