Summary of PCIE Hardware Design Pitfalls Based on XILINX FPGA

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Summary of PCIE Hardware Design Pitfalls Based on XILINX FPGA

With the continuous development of FPGAs, the number of built-in PCIE hard cores is increasing. This article introduces how to allocate the corresponding hardware pins using ZU11EG as an example.

Design goal: ZU11EG FFVC1760 package, with 4 sets of NVME, interface as PCIE X4.

First, we analyze the resources of ZU11EG. In UG1075, we can clearly see that it contains 4 PCIE blocks, located at X0Y2, X0Y3, XIY1, and XIY0.

Summary of PCIE Hardware Design Pitfalls Based on XILINX FPGA

In document PG213, we can see the following:

Summary of PCIE Hardware Design Pitfalls Based on XILINX FPGA

In summary: when allocating hardware design pins, we need to know:

1. A GT Quad consists of four GT lanes. When selecting GT Quads for PCIe IP, Xilinx® recommends using the GT Quad closest to the PCIe hard block. While this is not mandatory, it will improve the design’s position, routing, and timing.

2. Pay attention to the position of PCIE lane 0.

3. According to these tables, the tables determine which GT libraries are available based on the PCIe block position selected during IP customization.

Summary of PCIE Hardware Design Pitfalls Based on XILINX FPGA

How to verify your allocation results? Ultimately, in practical usage, we will apply the relevant IP cores. The simplest and most reliable method is to create a new project in Vivado and generate the PCIe IP core for verification, as shown in the figure below, where you can clearly see which ones are available.

Summary of PCIE Hardware Design Pitfalls Based on XILINX FPGA

In FPGA hardware design, pin allocation is the most important and critical step.

Summary of PCIE Hardware Design Pitfalls Based on XILINX FPGA

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Summary of PCIE Hardware Design Pitfalls Based on XILINX FPGA

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Summary of PCIE Hardware Design Pitfalls Based on XILINX FPGA

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Summary of PCIE Hardware Design Pitfalls Based on XILINX FPGA

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Summary of PCIE Hardware Design Pitfalls Based on XILINX FPGA

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Summary of PCIE Hardware Design Pitfalls Based on XILINX FPGA

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