In this article (Implementing a PCIe Device in Qemu: Adding DMA Functionality), we added a vector addition feature to the PCIe device simulated with Qemu. This PCIe device uses DMA read operations to transfer the contents of two operand vectors provided by the driver into an internal buffer of the PCIe device, computes the sum … Read more
In the article on interrupt handling in drivers, we introduced how to add logic for handling periodic Timer interrupts in the driver for our simulated PCIe device. To test the Timer counting functionality, we also created a user-space test program that reads the Timer’s count register every second. While this approach can test whether the … Read more
In the previous article (Implementing a PCIe Device in Qemu: Adding a Periodic Timer to the Device), we introduced how to add a Timer to a PCIe device simulated by Qemu. This Timer has a counter that increments by 1 every second once enabled, and it also sends an interrupt to the virtual machine.To test … Read more
In this article, we add a periodic Timer to the PCIe device previously simulated in Qemu. Once this Timer is enabled, it will trigger an MSI interrupt to the Qemu virtual machine every second. To verify that this interrupt function works correctly, we need to add interrupt handling capabilities to the driver for this PCIe … Read more
To add more functionality to the PCI device driver we wrote, we simulated a test PCIe device on QEMU, allowing us to implement features we wanted, such as DMA and interrupts. For the specific implementation of this PCIe test device, please refer to How to Implement a PCIe Device in QEMU. The Vendor ID and … Read more
Recently, while simulating MSI-X interrupts using QEMU, I found that many people do not fully understand MSI-X interrupts. Below, I will analyze this based on the Linux kernel version 6.1.26 source code. 1. MSI-X Specification in the PCIe Protocol 1.1 MSI-X Capability in PCIe Configuration Space Capability According to the PCIe 3.0 specification, the MSI-X … Read more
When designing PCBs, the design requirements for common hardware interfaces are crucial for ensuring circuit performance and stability. Below are some common hardware interface PCB design requirements: 1. USB Interface Design Requirements ① Total length control: Keep it within 1800 mils as much as possible. ② Differential pair characteristic impedance: 90Ω. ③ Power pin trace … Read more
In the previous article, we introduced the driver code generated by the VS KMDF template, providing a preliminary understanding of the driver code. It should be evident that this driver is quite simple, essentially lacking any real functionality. After installing the driver we wrote, this PCIe device remains in the D0 state (if you are … Read more
The Xilinx DMA/Bridge Subsystem for PCI Express (PCIE) IP (XDMA) significantly reduces the difficulty for FPGA developers in using the PCIE interface. By implementing a simple BD design, FPGA-side logic design can be achieved, and with open drivers and example code, developers can quickly establish end-to-end communication over PCIE.Currently, Xilinx has released drivers for XDMA … Read more
Project Name: Handcrafted 10G Soft Router NAS, using only LattePanda Mu PCIe board Project Author: Mr. Light Up Introduction This is an extremely powerful expansion board! It is equipped with 3 PCIe slots, supporting: 10G Network Cards NVMe Expansion Cards Graphics Cards, etc. Various PCIe Devices One board achieves network acceleration, storage expansion, and local … Read more