1. I2C Devices 1.1 I2C Controller Description of the I2C bus controller node: i2c0: i2c@10002000 { compatible = "arm,versatile-i2c"; reg = <0x10002000 0x1000>; interrupts = <0 30 4>; #address-cells = <1>; #size-cells = <0>; clocks = <&osc24M>; clock-frequency = <100000>; /* 100KHz standard mode */ status = "okay"; }; Key Attribute Descriptions: <span>#address-cells = <1></span>: … Read more
1. Core Background: The “Extended Tag Field” Option of PCIe IP Core – When instantiating the Xilinx V7 series PCIe Endpoint (EP) IP core in the Vivado tool, you will encounter the configuration option “Extended Tag Field”, which is directly related to the bit width of the TAG number: – If this option is checked: … Read more
RZ/T2H This article discusses the RZ/T2H’s PCIe peripheral functioning as an Endpoint (EP) and the potential issues that may arise when developing drivers and conducting speed tests on Windows, particularly the problem of Windows not recognizing the device. It summarizes various debugging methods and techniques to identify and resolve these issues. As shown in the … Read more
Follow and star our public account for exciting content delivered daily. Source: Online materials Introduction: Xilinx FPGAs are commonly used in serial communication interface design due to their high performance and low latency. This article provides an in-depth analysis of three key serial communication protocols in Xilinx system design: Aurora, PCI Express, and Serial RapidIO. … Read more
RK3588 is Rockchip’s flagship SoC, its PCIe controller, with flexible link splitting capabilities and rich features, has become the core bridge for connecting peripherals such as NVMe, WiFi, AI acceleration cards, etc. This article integrates hardware resource analysis, practical split configuration schemes, key configuration steps, and pitfall points, along with a visual mind map, to … Read more
[Image] With the rapid rise of AI technology, the demand for data bus throughput in servers and computing devices has shown exponential growth. Taking the PCIe standard as an example, to meet the computational power requirements of AI, its protocol has been upgraded to PCIe 5.0/6.0, with signal frequencies breaking through 32GT/s and approaching 64GT/s. … Read more
1 ARI (Alternative Routing-ID Interpretation) 1.1Technical Background To understand ARI, it is essential to grasp the traditional routing ID limitations of PCIe. A PCIe request (such as Memory Read/Write) consists of three parts in the Requester ID: Bus Number (8 bits), Device Number (5 bits), Function Number (3 bits) In traditional mode, a PCIe device … Read more
Everyone knows that the Linux kernel has a very wide range of applications, permeating many fields of life and production. In the consumer electronics sector, it supports numerous products such as smartphones, smart TVs, smartwatches, and smart locks, enabling functions like communication, entertainment, and health monitoring. In industrial scenarios, industrial PLCs, in-vehicle infotainment systems, and … Read more
In early 2024, based on project requirements, the read and write functionality of SATA hard drives was developed on the K7 board. At that time, considering future board upgrades, higher-speed PCIe NVMe M.2 hard drives could be used. Relevant information was researched: a project from Hanyang University was referenced for related design. This experiment is … Read more
Since its debut in 2000, the SD (Secure Digital) memory card has become the most widely used portable storage medium globally. From digital cameras, smartphones, drones, single-board computers, to the latest portable gaming consoles, SD cards are ubiquitous. According to official data released by the SD Association (http://www.sdcard.org/) on May 21, 2025, the total number … Read more