Friends involved in IC design and verification know that simple single-core MCU code is everywhere. However, if you want to advance and study Multi-core Boot, Bus Arbitration, Cache Coherence, or Deadlock Detection, having a reliable multi-core RTL source code is essential. Without it, even the most skilled craftsman cannot cook without rice. At the end of this article, I will provide a link to the project source code on Baidu Cloud. I recommend the following article.ARM Cortex-M3 DesignStart Series – 1 Functional Simulation + Official ARM Open Source Code and Compiler
Today, I will summarize 5 top SoC projects recognized by both industry and academia. They not only have cores but also buses, peripherals, and even complete UVM environments. Whether you want to study high-performance RISC-V architectures or build an ARM dual-core system yourself, this list will meet your needs.
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1. Performance Monster: Rocket Chip + LiteX Ecosystem
If you want to play big, go directly for high-performance RISC-V multi-core; this combination is currently the pinnacle of the open-source world. Rocket Chip provides the core, while LiteX offers an extremely rich peripheral ecosystem.
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Core Engine: Rocket Chip (or Boom)
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Supports generating 1 to 4 cores (or even more) RV64GC architecture.
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Optional Out-of-Order Execution Boom core, with clock frequencies exceeding 1GHz under ASIC.
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Native support for TileLink coherence bus, which is a standard textbook for studying the MESI cache coherence protocol.
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Peripheral Framework: LiteX
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This is a powerful SoC building tool that can automatically mount a rich set of high-speed interfaces.
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Interface List: Ethernet (GbE), USB 3.0, PCIe, DDR3/4/5 controllers, SATA, HDMI, etc.
Verification Topics from the Editor’s Perspective:
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PCIe and DMA Interaction: Using the PCIe interface generated by LiteX, verify the data transfer between the host and multi-core SoC, observing whether the CPU is starved by the bus during large data transfers.
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SMP Linux Boot: Running Linux on a 4-core Rocket, capturing the IPI (Inter-Processor Interrupt) waveforms during the boot phase, and analyzing how Core 0 wakes up other cores.
🔗 Download Links:
Rocket Chip:https://github.com/chipsalliance/rocket-chip
LiteX:https://github.com/enjoy-digital/litex
2. Academic Benchmark: PULPissimo (PULP Platform)
A project from ETH Zurich, focusing on ultra-low power and parallel computing, with a very advanced architecture.
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Core Configuration: Heterogeneous Architecture
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Utilizes a Fabric Controller (FC) + Cluster design.
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The main core is responsible for control, while the Cluster contains multiple (4/8) RISC-V computing cores (RI5CY/CV32E40P).
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Design Highlights:
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uDMA (Micro-DMA): Directly sends peripheral data to L2 memory without occupying CPU cycles.
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Shared L1 Memory: Multi-core within the Cluster shares L1 TCDM memory library.
Verification Topics from the Editor’s Perspective:
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L1 Memory Bank Conflict: Multiple cores within the Cluster share L1 memory. Write code to allow different cores to access the same Memory Bank simultaneously, capturing waveforms to observe how the bus arbiter handles conflicts (even pausing the pipeline).
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AXI to Cluster Bridging: Analyze how external AXI transactions are converted into the Cluster’s internal Logarithmic Interconnect.
🔗 Download Links:
GitHub:https://github.com/pulp-platform/pulp
3. Industrial Verification: OpenHW Group CORE-V MCU
If you are a verification engineer looking to enhance your skills, this project is a must-see. It is backed by major companies like NXP and Thales, featuring a verification environment closest to commercial standards.
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Core Configuration: CV32E40P (an industrial-grade core based on the improved PULP RI5CY).
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Although the reference design defaults to a single core, its bus architecture supports expansion to multiple Masters, and there are community discussions on this.
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Design Highlights:
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core-v-verif: This is an extremely complete verification environment based on UVM (Universal Verification Methodology).
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Includes a complete set of Agent, Scoreboard, Coverage Model.
Verification Topics from the Editor’s Perspective:
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UVM Environment Practice: Teaching how to run a UVM Regression for an open-source core.
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Interrupt Virtualization Verification: Using its Event Unit, verify how external GPIO interrupts are routed to the CPU, and write SystemVerilog Assertions (SVA) to check interrupt response timing.
🔗 Download Links:
GitHub:https://github.com/openhwgroup/core-v-mcu
UVM Environment:https://github.com/openhwgroup/core-v-verif
4. Textbook-Level Project: The NEORV32 Processor
If you want to avoid the hassle of complex generator scripts and just want to see pure hand-written code, NEORV32 is the best choice. The code is as clear as a textbook.
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Core Configuration: SMP (Symmetric Multi-Processing)
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Can be configured to dual-core mode with a single click using VHDL Generic parameters.
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Both cores share the bus and all peripherals.
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Complete Peripheral Set: Includes UART, SPI, TWI, GPIO, Watchdog, PWM, TRNG (True Random Number Generator), CFS.
Verification Topics from the Editor’s Perspective:
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Atomic Instruction (AMO) Implementation: How is the
<span><span>LR/SC</span></span>instruction implemented using a simple bus lock mechanism? This is very suitable for writing an analysis article. -
JTAG Debugging Multi-Core: It comes with a complete On-Chip Debugger, which can verify how the debugger separately “pauses Core 0” while allowing “Core 1 to continue running”.
🔗 Download Links:
GitHub:https://github.com/stnolting/neorv32
5. Classic Modification: ARM Cortex-M3 Dual-Core DIY
If you want to study the ARM architecture but are struggling to find source code, this is currently the only legal way to “get it for free” in RTL.
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Core Resources: ARM DesignStart Eval
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ARM officially provides obfuscated RTL for Cortex-M3 (simulatable and synthesizable).
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System Architecture: CMSDK (Cortex-M System Design Kit)
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Includes basic components such as AHB/APB bridges, UART, Timer, etc.
Challenge Task: Handcrafting Dual-Core
You need to modify the top-level design of CMSDK to instantiate two Cortex-M3 on the AHB Matrix and manually handle the arbitration logic.
Verification Topics from the Editor’s Perspective:
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Self-Made Dual-Core Mutual Exclusion: Cortex-M3 does not have AXI Exclusive Access. Try to implement a software mutual exclusion algorithm (like Peterson’s algorithm) using shared SRAM between the two cores, and use waveforms to prove its correctness.
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AHB Bus Locking: Analyze the behavior of the M3’s
<span><span>HMASTLOCK</span></span>signal during the execution of the<span><span>SWP</span></span>(Swap) instruction, observing how it monopolizes the bus.
🔗 Access Method:
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ARM Cortex-M3 DesignStart Series – 1 Functional Simulation + Official ARM Open Source Code and Compiler
Conclusion
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If you want to play with the latest Linux multi-core 👉 Rocket Chip + LiteX
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If you want to learn professional UVM verification 👉 OpenHW CORE-V
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If you want to study heterogeneous and DMA 👉 PULPissimo
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If you want to see a clear SMP implementation 👉 NEORV32
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If you want to delve into ARM fundamentals 👉 Cortex-M3
Verification is not something you can learn just by reading; you need to actually debug. Pick one that looks good, and start setting up the environment this weekend!
Access to Materials
Follow the WeChat public account “Chip Verification Diary” and reply “soc20251125” to obtain the Baidu Cloud link for the materials below.
