First Experience with Xilinx HLS

Why is it called “Xilinx HLS”? It is said that Altera’s HLS is somewhat different.

1 HLS Design

The names of Xilinx’s HLS tools vary; I recall “Vivado HLS” and “Vitis HLS”. The version of the tool I used is 2024.2, and this version of the HLS tool is called “Vitis”. Vitis 2024.2 is a unified IDE, and HLS is one of its features. Please enjoy the interface; the code is also included, and you can zoom in to see it better.

First Experience with Xilinx HLS

Yes, this is not VSCode.

This segment of C++ code is designed to invert a grayscale image with a resolution of 1920*1080 (grayscale inversion). This is quite simple, and simulation is not very necessary. “C SYNTHESIS -> Run” synthesizes to HDL, saved in “Output/impl/(verilog | vhdl)”. “PACKAGE -> Run” packages the IP Core, and the save path is “Output/ip/xilinx_com_hls_hls_gray_reverse_1_0.zip”.

First Experience with Xilinx HLS

To learn Xilinx HLS, refer to the manual “UG1399 – Vitis High-Level Synthesis User Guide”, note that there is a Chinese version available.

2 Verification

Add the IP Core to Vivado by navigating to “tools -> settings -> Project Settings -> IP -> Repository”.

First Experience with Xilinx HLS

“data[63:0]” is the address offset for the m_axi_gmem interface. ap_ctrl is the start signal and status signal for the IP Core (both are logic signals, without complex protocols). The synthesis generates a bitstream, exports the XSA, and then runs petalinux-config, petalinux-build, petalinux-package, and starts Linux/ZYNQ.

Write a segment of Python or C code to write the grayscale image into the memory indicated by “data[63:0]”, start the computation using ap_ctrl_start, and wait for ap_ctrl_done to indicate completion. The IP Core modifies the image in place, so read the inverted image from the memory indicated by “data[63:0]”.

First Experience with Xilinx HLSFirst Experience with Xilinx HLS

The image above is the original image, and the image below is the inverted grayscale image.

3 My Thoughts on HLS

I used to think HLS was immature, and I would never use it. Later, considering computational acceleration, I felt it was necessary to understand HLS/OpenCL. Now that I have experienced it, especially the direct generation of AXI interfaces, it is quite appealing.

HLS has characteristics that differ from HDL, and HDL also has its own advantages. Currently, it seems that without requiring HLS to replace HDL, HLS should be a good option.

** Complementing strengths and seeking common ground while reserving differences **

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