Design Tools and Workflow for RFSoC SDR – PL Design: Creating Custom IP

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Translation of Chapter 13 from the compilation “RFSoC-Book” is detailed in the first article of this series.

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For designers, it is crucial to efficiently build custom hardware functions for specific applications or systems. Designers can create their own custom IP core repositories and import these user-designed IPs into Vivado for integration into the IPI system design.There are various methods for creating IP cores. By using high-level software languages such as C/C++, or graphical modular design tools, a higher level of abstraction can be provided over traditional HDL design. The main advantage of using these higher abstraction levels is the significant reduction in design cycles, thereby lowering development costs and accelerating time to market.The remainder of this section will introduce various methods for creating IP cores, including official AMD tools and third-party solutions. Some third-party tools also integrate with Vivado in the background to support the IP creation process.

• HDL Code DevelopmentThe traditional hardware development method involves writing code using mainstream HDLs (VHDL, Verilog) or SystemVerilog (a superset of Verilog that adds verification capabilities). The HDL description defines the design’s interfaces and functionalities, and typically requires writing a testbench for verification. The developed HDL IP cores can be completed in the Vivado IDE for development and simulation. HDL languages support hierarchical design, making modular development, testing, and integration easier, and allowing for the reuse of existing modules. The main drawback of HDL development is its high design cost and long time consumption. Even though HDL provides a high level of design control, the development process is still highly dependent on specialized skills and involves a significant workload. The tools and methods introduced later in this section enhance the design level compared to HDL, thus providing a significant efficiency boost. It is important to note that these advanced tools still generate HDL code in the background.
• Vitis High Level Synthesis (HLS)Vitis HLS is an AMD tool that can be installed alongside Vivado, supporting the conversion of C/C++ functions into IP cores. By introducing pragma directives (comment-based compilation instructions) in the code, the tool can automatically restructure C code to meet hardware design goals (such as maximizing throughput or minimizing latency). Therefore, designers can first implement the desired functionality in pure software, compile, simulate, and debug it, and then synthesize it into a hardware IP core. Since Vitis is tightly integrated with Vivado, developers can directly generate IP core repositories compatible with the Vivado version in Vitis HLS.

• HDL Coder and SoC BlocksetMathWorks’ HDL Coder is another hardware design tool based on the MATLAB and Simulink environment. With HDL Coder, HDL code can be generated from compatible MATLAB functions and modular models in Simulink for creating IP cores that can be used in Vivado. The later Figure 13.17 shows a simple design example using HDL Coder.After configuring HDL Coder at the start of the design, MATLAB and Simulink will establish a connection with the supported version of Vivado, enabling tool integration that allows users to automate the entire design process within the MathWorks environment. Its main interface is the HDL Workflow Advisor, a wizard-like tool for top-level models that assists in generating HDL. This method also facilitates mapping the model’s IO to the AXI4 input/output interfaces of the generated IP core.The functionality of HDL Coder can be further extended through the SoC Blockset. The SoC Blockset adds FPGA memory, peripheral IO, PS scheduling-related modules, and hard resources for RFSoC (such as RFDC) to Simulink. These modules can also generate HDL, allowing for the creation of complete Vivado Block Designs directly through Simulink. The SoC Blockset is tightly coupled with the SoC Builder (which will be further introduced in Section 13.4). When using the SoC Blockset, the design elements of PS and PL can be combined as a single Simulink model; in conjunction with the SoC Builder, hardware-software co-design can be achieved to build a complete RFSoC embedded system.
• Model ComposerAMD provides its own modeling HDL design tool in the Simulink environment: Vitis Model Composer. This tool can optionally be installed alongside Vivado and includes over 200 function modules maintained by AMD that can be directly used for HDL generation. Designers can also import custom modules, including hand-written VHDL/Verilog modules or modules developed through Vitis HLS. This allows users to build IP cores that contain both library modules and custom modules, and export them to hardware after simulation.Model Composer offers HDL synthesizable modules specifically designed for DSP applications, including FIR filters, FFT, and trigonometric function operation modules based on the CORDIC algorithm. These modules are hardware-optimized, providing implementation options that allow designers to customize according to specific PL architecture resources (such as DSP48E2 arithmetic units and Block RAM).

• Open Source HDL Generation SolutionsThe open-source community also provides some alternative HDL and IP core generation tools. Clash is a high-level HDL that borrows syntax rules from Haskell and maps to VHDL and/or Verilog at compile time. MyHDL and Amaranth are Python-based projects that adopt a similar approach, converting to VHDL or Verilog during the compilation phase. Chisel is conceptually similar to Vitis HLS, but it achieves this by adding pragmas that generate HDL in the Scala programming language (instead of using C/C++). Chisel supports reusable HDL descriptions while providing register-level coding capabilities, enhancing the design’s abstraction level while retaining low-level control. It is important to note that these open-source tools are maintained by the community and typically offer less guidance on the IP core generation process compared to the commercial tools mentioned earlier.