Six years ago, Intel, the market leader in CPUs, acquired Altera, the second-largest FPGA company.This month, AMD, the second-largest CPU market player, completed its acquisition of Xilinx, the leading FPGA company.
Now, visiting Xilinx’s official website reveals that following AMD’s acquisition of Xilinx, they aim to create an industry leader in high-performance and adaptive computing.Coincidentally, six years ago, Xilinx launched the Zynq UltraScale+ MPSoC, which is a comprehensive upgrade from the first-generation Zynq-7000. It provides complete flexibility at both hardware and software levels, offering not only 64-bit processor scalability but also combining real-time control with hardware and software engines to support graphics, video, waveform, and packet processing.
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Zynq UltraScale+ MPSoC
The heterogeneous combination mode of Zynq UltraScale+ MPSoC greatly enhances product scalability, adding multiple processor cores, video processing, and other functional modules at a lower cost, providing excellent cost-performance ratio.Zynq UltraScale+ MPSoC includes three different variants, each with its focus: dual-core application processor (CG) devices, quad-core application processors and GPU (EG) devices, and video codec (EV) devices. All three variants have multiple chips with varying performance for users to choose from.Specific selection documents and reference materials can be obtained by sending the keyword “MPSoC” to the “Hardware and Software Technology Development” WeChat public account.
Zynq UltraScale+ MPSoC offers various interconnect options, DSP modules, and programmable logic choices, thus providing overall flexibility to meet various user application needs.
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Main Features of PS
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A quad-core 64-bit ARM Cortex-A53 processor with L1 and L2 cache and ECC functionality, capable of powering on and off independently;
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The Cache coherence interconnect unit provides bidirectional Cache coherence guarantees for PS and PL;
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The SMMU (System Memory Management) unit is used for virtual memory management of PS and PL;
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A dual-core ARM Cortex-R5F processor (with floating-point extension) that can operate in lockstep or independently, includes Cache and ECC-enabled storage, and can be powered off in pairs;
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ARM Mali-400 MP2 GPU for 2D/3D graphics display, with DP interface supporting one or two 4Kp30 video streams;
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H.265/264 video codec, supporting 4Kp60 encoding and decoding at 10-bit pixel depth;
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Configuration and power management unit based on three redundant processors;
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DDR controller supporting ECC-enabled DDR3/4 and LPDDR3/4 SDRAM, with shared SDRAM space between PS and PL of Zynq UltraScale+ MPSoC;
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Hard peripherals include: GigE, USB3.0, SATA3.0, SPI, IIC, CAN, UART, and Flash controllers (QSPI-NOR, SD, eMMC, ONFI NAND).
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Applications in Software Radio
Whether for Land Mobile Radio (LMR) or Professional Mobile Radio (PMR), the mainstream trend is to use software-defined baseband architectures in new-generation products to provide multiple broadband modulation modes (LTE, TETRA), and even to offer various modulation modes simultaneously. This requires radio platforms to host data applications optimized for public safety or private networks.The Zynq UltraScale+ MPSoC series is very suitable for the public radio communication market. Battery-powered narrowband public safety radio devices are in standby mode 90% of the time, performing send or receive operations only 10% of the time.Software radio utilizes the integrated power domains and power islands in the MPSoC to turn off all unused systems. Waveforms from the input RF module are continuously monitored by a Cortex-R5 processor in the RPU, while other Cortex-R5s handle security tasks. The entire power domain, including APU and programmable logic, remains powered off, allowing the entire system’s power consumption to drop to as low as 35mW.
Once effective transmission is detected, the RPU wakes up the APU and programmable logic through inter-processor interrupts. Then, the programmable logic immediately begins processing RSSI authentication, filtering, and packet header decryption. Following transmission authentication, a Cortex-A53 processor in the APU starts Vocoder processing, utilizing its integrated next-generation SIMD for the fastest performance. Meanwhile, another Cortex-A53 has already awakened the display.The third Cortex-A53 is ready to handle Android applications. The APU processor can achieve fully asymmetric operation through a manager and can be gate powered off using power islands when not in use. The integrated VCU can also be used for encryption/decryption and offline storage of signals when necessary.With various multiprocessors and hardened engines within the Zynq UltraScale+ MPSoC, the RPU can continuously monitor and wait for applicable signals while keeping the remaining power domains in sleep mode to significantly reduce power consumption. With improvements in programmable logic and new lower-power memory interfaces, the performance-to-power ratio of Zynq UltraScale+ MPSoC has increased several times compared to existing software radio systems.
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Usage Tutorial
We will gradually release some tutorials related to Zynq UltraScale+ MPSoC, specifically on ZU7EV. Those who wish to learn together can add the editor’s WeChat “RCEW-Pro” to join the WeChat technical exchange group.
