Can Xilinx FPGA General IO Be Directly Connected to PLL as Clock Input?

[Conclusion]

General IO cannot be directly used as a clock input for PLL; dedicated clock pins can be used instead.

General IO can be connected to the PLL clock input through a BUFG, but the PLL settings must be modified to select “No Buffer” for the input clock option.

The specific internal layout can be viewed using Xilinx’s FPGA Editor.

The clock management in ZYNQ is slightly different from previous devices; relevant documentation can be found in <ug472_7Series_Clocking.pdf>

Link: https://pan.baidu.com/s/1E2uZbeIGh8R8FaDUQ6XVFg

Extraction code: open

[Demo1]

// demo1 two bufg connect
module iobuf(
 input clk,
 input rst,
 output led
);
 wire clkin_w;
 BUFG BUFG_inst (
      .O(clkin_w),           // Clock buffer output
      .I(clk)                   // Clock buffer input
   );
 pll0 u_pll0(
    .CLK_IN1(clkin_w),      // IN
    .CLK_OUT1(clkout),  // OUT
    .RESET(rst));       // IN
assign led = clkout;
endmodule

The phase-locked loop (PLL) has a default input front end with a BUFG unit, and two BUFGs cannot be connected in series, which will result in the following error:

ERROR:NgdBuild:770 – IBUFG ‘u_pll0/clkin1_buf’ and BUFG ‘BUFG_inst’ on net

‘clkin_w’ are lined up in series. Buffers of the same direction cannot be

placed in series.

ERROR:NgdBuild:924 – input pad net ‘clkin_w’ is driving non-buffer primitives:

[Demo2]

// demo2 regular io directly connect to PLL
module iobuf(
    input clk,
 input rst,
 output led
 ); wire clkin_w;
 /*
 BUFG BUFG_inst (
      .O(clkin_w),           // Clock buffer output
      .I(clk)                   // Clock buffer input
   );
*/
 pll0 u_pll0(
    .CLK_IN1(clk),      // IN
    .CLK_OUT1(clkout),  // OUT
    .RESET(rst));       // IN
assign led = clkout;
endmodule

General IO cannot be directly used as an input for the phase-locked loop, which will result in the following error:

ERROR:Place:1397 – A clock IOB / MMCM clock component pair have been found that

are not placed at an optimal clock IOB / MMCM site pair. The clock IOB

component <clk> is placed at site <A18>. The corresponding MMCM component

<u_pll0/mmcm_adv_inst> is placed at site <MMCME2_ADV_X0Y0>. The clock IO can

use the fast path between the IOB and the MMCM if the IOB is placed on a

Clock Capable IOB site that has dedicated fast path to MMCM sites within the

same clock region. You may want to analyze why this problem exists and

correct it. If this sub-optimal condition is acceptable for this design, you

may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this

message to a WARNING and allow your design to continue. However, the use of

this override is highly discouraged as it may lead to very poor timing

results. It is recommended that this error condition be corrected in the

design. A list of all the COMP.PINs used in this clock placement rule is

ERROR:Pack:1654 – The timing-driven placement phase encountered an error.

If you add this constraint in the ucf:

NET clk          CLOCK_DEDICATED_ROUTE = FALSE;

It will still report an error. In the ZYNQ7000 series, this will not pass, as follows:

ERROR:PhysDesignRules:2256 – Unsupported MMCME2_ADV configuration. The signal

u_pll0/clkin1 on the CLKIN1 pin of MMCME2_ADV comp u_pll0/mmcm_adv_inst with

COMPENSATION mode ZHOLD must be driven by a clock capable IOB.

ERROR:Pack:1642 – Errors in physical DRC.

Using a general IO and then connecting it to the clock line through a BUFG will still report such errors, as two BUFGs are connected:

ERROR:NgdBuild:770 – IBUFG ‘u_pll0/clkin1_buf’ and BUFG ‘BUFG_inst’ on net

‘clkin_w’ are lined up in series. Buffers of the same direction cannot be

placed in series.

ERROR:NgdBuild:924 – input pad net ‘clkin_w’ is driving non-buffer primitives:

[Demo3]

// demo3 regular io with BUFG then connect to PLL which with "No Buffer" setting
 module iobuf(
 input clk,
 input rst,
 output led
 );
 wire clkin_w;
 BUFG BUFG_inst (
      .O(clkin_w),           // Clock buffer output
      .I(clk)                   // Clock buffer input
   );
 pll0 u_pll0(
    .CLK_IN1(clkin_w),      // IN
    .CLK_OUT1(clkout),  // OUT
    .RESET(rst));       // IN
assign led = clkout;
endmodule

The PLL settings are shown in the following image,

Thus, general IO can be used as a clock input for the PLL, successfully generating a bitstream;

It is still best to use global clock IO; be sure to pay attention when drawing.

In ZYNQ7020, there is no concept of a global clock, but there are many dedicated clock pins, which can be used similarly.

The article is adapted from: https://suisuisi.blog.csdn.net/article/details/112854131Copyright belongs to the original author.

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