FPGA Clock Analysis The clock system is the “heart” of FPGA design, and its performance directly determines the system’s timing margin, operating frequency, and stability. Effective clock analysis can help engineers identify timing bottlenecks, optimize clock architecture, and ensure reliable operation of the design at the target frequency. This article will systematically analyze the composition, … Read more
Click the blue text to follow, grateful for your support Welcome friends to follow“Hao Xushuang Electronic Design Team” public account, this account will regularly update relevant technical materials, software, etc. Friends who are interested can browse other“modules”, hoping that everyone can gain something they want from this public account. This article mainly discussesClock Resources in … Read more
In microcontrollers, the STM32F103 is powerful and widely used. To ensure the stable operation and performance optimization of the STM32F103 system, configuring its clock system is essential. So, how do we configure it? 1. Clock Source Selection HSI: Internal RC oscillator with a frequency of 8MHz, suitable for situations where clock frequency accuracy is not … Read more
Zha Tianyi1, Chen Shengqi2, Ge Junyao3 (1. Changshu High School, Jiangsu Suzhou 215500; 2. Department of Electrical Engineering and Applied Electronic Technology, Tsinghua University, Beijing 100084; 3. School of Communication and Information Engineering, Nanjing University of Posts and Telecommunications, Jiangsu Nanjing 210023) Abstract: This paper adopts the fractional-N phase-locked loop (PLL) chip ADF4351 as the … Read more
Introduction: From this article onwards, we will successively introduce the clock resource architecture of Xilinx 7 series FPGA. Mastering clock resources is very important for both FPGA hardware design engineers and software design engineers. This chapter provides an overview of the 7 series FPGA clocks, compares the differences between the 7 series FPGA clocks and … Read more
In modern SoC (System-on-Chip) design, the CRG (Clock and Reset Generator) serves as the “heart” and “nervous system” of the entire chip, responsible for providing stable, reliable, and controllable clock and reset signals for the system. The quality of the CRG module’s design directly affects the chip’s functional correctness, power consumption performance, testability, and overall … Read more
13.2.2.2 PLL2 Phase-Locked Loop The PLL output is mainly used for system clock (ICLK) and others, while PLL2 is primarily used for some important peripherals, providing them with a stable clock separately. Here, we do not use PLL2. PLL2 section in the FSP clock configuration diagram: 13.2.3 System Clock Area See the marked area ③ … Read more
13.2.1 Clock Sources 13.2.1.1 External Oscillator Clock Area The external oscillator includes an external high-speed oscillator (main clock oscillator) and an external low-speed oscillator (sub-clock oscillator). Main Clock Oscillator (MOSC): Main clock oscillator RA6M5/RA4M2 connects to an external 8~24MHz high-speed crystal oscillator (connected to pins EXTAL, XTAL); RA2L1 connects to an external 1~20MHz high-speed crystal … Read more
This article elaborates on the core components and importance of the clock system in microcontrollers (MCUs). It points out that the performance and power consumption of an MCU fundamentally depend on its clock system. This system is based on a clock source (external crystal oscillator or internal RC oscillator) and distributes signals to various modules … Read more
[Conclusion] General IO cannot be directly used as a clock input for PLL; dedicated clock pins can be used instead. General IO can be connected to the PLL clock input through a BUFG, but the PLL settings must be modified to select “No Buffer” for the input clock option. The specific internal layout can be … Read more