Canaan Technology’s Multiple Chip Customization Projects Enter Design Phase, Expected to Tape Out This Year

Canaan Technology's Multiple Chip Customization Projects Enter Design Phase, Expected to Tape Out This Year

According to news from the semiconductor industry, on June 10, Canaan Technology stated during an institutional survey that multiple chip customization projects have entered the design phase in the first quarter of 2025 and are expected to tape out within this year. The company provides design services for an MRAM control chip project, which is … Read more

Clock Design for MCU Chips

Clock Design for MCU Chips

For general-purpose MCU chips, the CPU operating frequency ranges from 100 to 300 MHz, while the frequency of typical crystals (xtals) is usually in the tens of MHz range. Therefore, MCUs typically use a PLL module to multiply the frequency to the hundreds of MHz range.Similarly, taking the STM32F10xxx series as an example, let’s examine … Read more

Issues Caused by Frequency Offset in FPGA-PLL Outputs

Issues Caused by Frequency Offset in FPGA-PLL Outputs

Follow and star our public account for exciting content delivered daily. Source: Online materials We are still debugging an image issue where one chip exhibits a flickering phenomenon in the output image. The system is initially defined as follows: Explanation: (1) A 24MHz crystal oscillator outputs a clock that is fed into the FPGA and … Read more

Eliminating Jitter Significantly Improves SoC Performance

Eliminating Jitter Significantly Improves SoC Performance

Author Introduction Dr. Liu, Ph.D. from University of Electronic Science and Technology, an expert in microarchitecture. 1. Background The clock circuit is the most basic circuit in the chip. The performance of the clock circuit is related to whether all the modules in the SoC can achieve the expected goals, such as the main frequency … Read more

Introduction to FPGA Internal Resources: Clock Processing Unit

Introduction to FPGA Internal Resources: Clock Processing Unit

The third installment of the basic knowledge of FPGA internal resources is here! Today we will discuss the FPGA clock processing unit module. The clock is the soul of logic, so the clock signal is very important, take note!!Look me~ 1. PLL PLL, the full English name is Phase Locked Loop, which translates to Chinese … Read more

Passive Crystals vs Active Oscillators in DSP Circuit Design

Passive Crystals vs Active Oscillators in DSP Circuit Design

1、Passive Crystals——Passive crystals require an oscillator within the DSP chip, with recommended connection methods provided in the datasheet. Passive crystals do not have voltage issues; the signal level is variable, meaning it is determined by the oscillation circuit. The same crystal can be used for various voltage requirements, making it suitable for DSPs with different … Read more

Understanding STM32 Clocks

Understanding STM32 Clocks

Introduction to STM32 Clock Sources 1. The main clock sources of STM32 are: Internal Clock External Clock Phase Locked Loop (PLL) Frequency Multiplier Output Clock 1.1 Detailed Introduction HSI (Internal High-Speed Clock) It is an RC oscillator with a frequency of up to 8MHz, which can be used as the system clock and PLL input. … Read more

A Comprehensive Guide to LCD Screen and MIPI-DSI Parameter Calculation

A Comprehensive Guide to LCD Screen and MIPI-DSI Parameter Calculation

Introduction As an important part of the functionality of the i.MX series chips, we will be detailing the workings of display-related modules based on the i.MX8MP over the coming period, including the steps to enable customized screens and potential issues that may arise. This article will focus on MIPI-DSI, further calculating the parameters required for … Read more