If you want to create a SOC chip, self-develop customized IPs to highlight differentiation, while purchasing general-purpose IPs and simply connecting them, making a SOC is just about connecting the dots. Once the Verilog code is finished, is the chip ready for tape-out? Let’s not even discuss the technology of connecting the SOC; what happens after everything is connected?
First, you need to compile successfully, organize the file list, sub-modules, subsystems, and top-level, integrating from the bottom up. Run the RTL compile, clearing all errors. Once the compilation passes, clear all warnings. No errors, no warnings!
Then you need to clear Lint, cleaning sub-modules, subsystems, and top-level, eliminating all errors and warnings, and waiving those that cannot be cleared. No errors, no warnings!
Why aim for no warnings? Because many bugs may be hidden in warnings; fixing them reduces the number of bugs during validation.
Release the version for validation.
Generate SDC, writing per block, with the top-level producing only the top SDC. Run pre-synthesis, clearing logs and reports of all errors, and scanning all warnings. Deliver the block and the top. The top-only pre-synthesis should include the block’s lib/db; to expedite early delivery, a fake lib/db can be generated using scripts. The top can be delivered in parallel with the block. Deliver the sync cell list and don’t touch list.
Generate UPF, describing low power and power schemes, with block UPF, top-level UPF, and flat UPF. Produce the ISO list. Run CLP/VCLP to ensure UPF syntax and semantics are correct, and that domain divisions are conflict-free. Later, perform power analysis and optimization.
Run Formal verification, under normal circumstances, the RTL vs. netlist should pass in one go; if not, either your RTL has issues, or the synthesis constraints are unreasonable and need to be supplemented.
Run DFT VCLINT, write SGDC constraints, describing OCC points, test_rstn points, test mode, and clock mux points. Clear errors and warnings, which can resolve 80% of the uncontrolled issues with register clocks and resets in DFT mode. Deliver no scan list, no wrapper list, and TDR list.
Run CDC/RDC checks, per block, top-only, and full chip flat checks. Waive, no errors, no warnings!
Release the version to the mid-end.
In the middle and back end iterations, address DFT feedback issues by adding test_mux and TDR, supplementing unreasonable SDC constraints, increasing timing paths that are too long, and modifying RTL for congestion issues.
Validation debugging, EDA, EMU, FPGA, DFT, low power, and post-simulation validation debugging. Coverage analysis, producing waiver files to achieve “explainable” 100% coverage.
STA analysis, block STA, full chip flat STA. Produce flat SDC, modify unreasonable SDC, and iterate RTL for timing issues.
STC, special timing check, providing path checks to see if they meet expectations, and fixing violations.
RTL Freeze.
ECO, manual ECO or tool automated ECO flow.
Once the Verilog code is completed, is the chip ready for tape-out? Well, this is just the first step. Note: This article only covers front-end work; back-end work has not been addressed. To be continued~
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