Low Power Design Implementation Case Study | How to Avoid Misusing Always On Buffer in UPF Flow?

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The following diagram is a case from our community’s low power quad-core A7 Top Hierarchical Flow backend training camp, where there are several Power Domains in the design. Power Domain 2 (abbreviated as PD2) is the default Top Domain, Power Domain 1 (abbreviated as PD1) is a domain that needs to be powered off, and PD1 and PD2 are in the same Voltage Domain. Power Domain 3 is also a domain that needs to be powered off, and its operating voltage is VDD1.

For such low power design requirements, every digital IC backend engineer should be able to write the corresponding power intent constraint file, the UPF file.

This case is also very common in actual IC backend projects. Below, I will share some common issues based on this case.

1) Incorrect connection of the Secondary PG Pin of Always On Buffer

PD1 can use Aon Buffer internally, but its Secondary PG Pin can only be connected to the VDD net and cannot be connected to VDD1. The Innovus UPF flow supports automatic insertion of Aon Buffer and connects the secondary PG pin to the global VDD net.

However, the tools can easily encounter some issues, such as a signal from PD2 passing through PD1 and inserting several buffers/inverters, eventually passing out to PD2. But these buffers/inverters may be of the following situations:

• Common buffer/inverter

• Using Aon buffer but the secondary PG pin is connected incorrectly (the Aon buffer’s secondary PG pin in PD2 is connected to VDD1)

Essential for digital IC autumn recruitment written test and interview | Top ten soul-searching questions for low power design implementation

Therefore, to avoid this problem, we usually can prevent this signal from passing through PD1. The specific method can use UPF to constrain.

update_power_domain –name PD1 –user_attributes {disable_secondary_domains {PD2 PD3}}

create_power_domain PD1-supply {primary} -supply {extra_supplies “” } -include_elements

2) Always On Buffer in relation to Aon Domain

The yellow signal shown in the diagram below is a common signal in PD2, but after placement, it was found that there are many AON buffers and inverters on this net. Even though this PD2 is a power-off power domain, this signal only requires a common buffer.

If this situation occurs, the final low power verification clp or mvrc will report corresponding violations.

3) Common Buffer in Power Off Domain

In the low power design implementation of digital IC backend, we often encounter the timing path marked in green in the diagram below, where two common buffers are located within PD1. This clearly violates the power constraints of low power design implementation.

[Thinking Question] What should be the minimum spacing reserved between Power Domain 1 and Power Domain 3? Why?

When such situations occur, we need to carefully check the pst state descriptions in the UPF file to see if the switching scenarios of each power domain are described completely and accurately.

4) Routing issues across Power Domains

The following diagram shows a signal from cell B in PD1 connected to cell C’s input in PD3. This net crosses PD2 during routing, and when this net experiences max transition, it is difficult to fix.

Therefore, we need to control the tool routing by setting the following routing and opt modes. The diagram below shows the routing result after applying special routing constraint.

setRouteMode -earlyGlobalHonorMsvRouteConstraint true setNanoRouteMode -routeHonorPowerDomain true setOptMode -addAOFeedThruBuffer false

5) Principles for dividing shapes of various Power Domains

Below are several cases to share the principles that should be followed during the module partitioning process in low power backend design implementation.

Case 1: The shape of Power Domain should be as regular as possible

Generally, the shape of the power domain (sub-modules hardened separately) should be as regular as possible, especially for designs where timing and routing are not easy to handle.

The left side of the diagram shows a poor floorplan with many corners and narrow channels. The right side shows a relatively better module partitioning, but this L-shaped design is also prone to timing and routing issues at the corners.

Case 2: Avoid placing Macros or Blockages in the middle area of Power Domain

This is the principle we have always advocated for placing Macros – Macros should be placed at the boundaries of modules or Power Domains. Therefore, when partitioning modules or Power Domains, the internal Macro situation should be taken into account, especially for large Macros in width or height.

Case 3: Avoid thin channel PDs

Case 4: Avoid placing Default PD Memory at Power Domain boundaries

When the interface signal of PD1 needs to come out to interact with the Default PD at the lower left corner, the Macro at the boundary of PD1 will block the placement of standard cells and hinder the routing of interface signal lines.

Moreover, we know that the signals coming out of PD1’s interface also need to insert isolation cells. If these isolation cells are placed in the yellow area of the diagram, there will definitely be max transition violations. Unfortunately, the nets corresponding to these signals must also be set as dont touch.

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