✖ In 2024, Huawei continues to sponsor the China Graduate Innovation Competition, providing a total of nine corporate competition topics in the fields of RF, digital, analog, and EDA algorithms for participating teams to choose from. This year’s Huawei competition topic in the digital direction is: Model design and analysis simulation evaluation of side-channel attacks/fault … Read more
The typical ASIC design process can be divided into logical design and physical design. Logical design starts with high-level design specifications and chip architecture. The chip architecture describes high-level functionality, power consumption, and timing (the speed at which the design operates) requirements. This is followed by a description of the design at the register transfer … Read more
This article is one of the series blogs on “ASIC Design Learning” by EETOP user: tfpwl_lj Blog address: http://www.eetop.cn/blog/1638430 1. Low Power Design With the promotion of handheld portable devices, the issue of low power design has become increasingly important. Lower chip power consumption means longer usage time for handheld portable devices, reduced power consumption … Read more
Source: Future Dreamer WeChat Official Account Author: Sun Lu (Senior User of EETOP) Since I started university, my childhood friends and I have gone our separate ways for many years. Everyone has developed in their own way, working in different industries, and one by one, they have become experts. So, a classmate asked me, “You … Read more
EETOP focuses on chips and microelectronics, click the blue text above to follow us. Source:wikichip Celerity is an open-source multi-core RISC-V tiered accelerator chip created through the collaborative efforts of several universities. This project is part of DARPA’s Circuit Realization At Faster Timescales (CRAFT) program, which aims to reduce the design cycle of custom integrated … Read more
This article is part of the “ASIC Design Learning” series by EETOP user: tfpwl_lj. Blog address: http://www.eetop.cn/blog/1638430 1. Introduction For RTL-level ASIC design, there is a vast array of software involved, and the author has not used every single one. There is no need to elaborate further. 2. Tool Introduction RTL Code Rule Check Tools: … Read more
The complexity of ASICs is continuously increasing, and processes are constantly improving. Developing a stable and reusable ASIC chip design within a short time frame, and achieving a successful tape-out on the first attempt, requires a mature ASIC design methodology and development process. This article compares various ASIC design methods using EDA software such as … Read more
Many desktop computers do not have wireless network cards and can only connect via Ethernet. To use WiFi, you can simply plug in a USB wireless network card, which is convenient: The USB wireless network card is very compact, leading to curiosity about how the circuit board fits inside: Next, we will disassemble a model … Read more