This article is part of the “ASIC Design Learning” series by EETOP user: tfpwl_lj.
Blog address: http://www.eetop.cn/blog/1638430
1. Introduction
For RTL-level ASIC design, there is a vast array of software involved, and the author has not used every single one. There is no need to elaborate further.
2. Tool Introduction
RTL Code Rule Check Tools: nlint, spyglass. These two software are primarily used to check the syntax and semantic errors in the code, and they can detect more issues than other tools, such as naming specifications, timing risks, power consumption, etc. For detailed introductions, please refer to the software usage tutorials. nlint has versions for both Windows and Linux, and the usage tutorials can be found by searching on EETOP.
RTL Code Simulation Tools: There are many combinations of simulation tools, such as qustasim/modelsim, NC_verilog+Verdi, VCS+DVE, VCS+Verdi, etc. Currently, the author is using the combination of VCS+Verdi. These two software are mainstream simulation tools in the industry and can also be combined with the UVM library for simulation; of course, this is related to verification methodologies.
Synthesis Tool: Design Compiler. The most commonly used synthesis tool, by far, this software mainly “translates + optimizes + maps” RTL code into gate-level netlists corresponding to the process library. It also includes power analysis software Power Compiler and boundary scan register insertion software BSD Compiler.
Testability Design: DFT Compiler + TetraMAX. This software is used after DC, where DFT Compiler replaces the internal registers of the design with scan registers and forms one or more scan chains. TetraMAX is used to automatically generate test vectors.
Formal Verification Tools: Formality, Conforml (produced by Cadence). Equivalence verification tools, mainly used for verification after inserting scan chains with DFT Compiler. Additionally, during layout synthesis of clock trees, after inserting BUFFER, this tool is also required for equivalence verification.
Static Timing Analysis Tool: Prime Time. One of the most commonly used timing analysis tools in the industry, this software includes the power analysis tool PTPX, essential for power analysis. Cadence also has a corresponding timing analysis tool—Encounter Timing System.
Automated Place and Route Tools (APR): ICC, Encounter. Notably, Encounter is from Cadence.
Mixed-Signal Simulation: nanosim + VCS, where the upgraded version of nanosim is XA.
This is an introduction to Synopsys EDA tool software, and I hope it helps those who are unclear about the usage of EDA software. http://bbs.eetop.cn/thread-151171-1-1.html
3. Book Recommendations
“Verilog HDL Hardware Description Language”
“Design and Verification of Verilog HDL”
“Verilog Code Style Guidelines for Enterprises”
“Verilog Language Coding Style”
“Verilog HDL Code Style Guidelines”
“Advanced Digital Design with Verilog HDL”
“SoC Design Methods and Implementation”
“Advanced ASIC Chip Synthesis”
“Huawei Verilog Typical Circuit Design”
“Digital IC System Design”
“Digital Integrated Circuits—Circuits, Systems, and Design”
“Practical Tutorial on Application-Specific Integrated Circuit Design”
“Static Timing Analysis and Modeling of Integrated Circuits”
“Backend Design and Practice of CMOS Integrated Circuits”
“Makefile Tutorial”
“Bird Brother’s Private Kitchen”
“SystemVerilog and Functional Verification”
“UVM Practical”
“Communication IC Design (Volumes 1 and 2)”
“Digital Image Processing and Image Communication”
“FPGA Implementation of Digital Signal Processing (Chinese Edition)”
Various Synopsys user guides, EETOP has the 2016 version.
4. Process Library Explanation
Using DC, PT, FM, ICC, or ENCOUNTER software requires process library files, which mainly include digital logic unit files, symbol libraries, synthesis libraries, parasitic capacitance parameter libraries, layout files LEF, milkyway libraries, etc.
You can find explanations for certain process libraries on EETOP. http://bbs.eetop.cn/thread-611843-1-1.html Regarding the roles of various folders in the process library, the author will provide a detailed introduction in the chapter “Process Library Explanation”. If there are any omissions, please forgive me.
Welcome to visit the author’s EETOP blog: http://www.eetop.cn/blog/1638430
You can read more of the “ASIC Design Learning” series blogs.
We are fortunate to invite several well-known companies and institutions from the TOP20 list, including ARM, Huawei, ZTE, Keysight Technologies, Alibaba, etc., to attend the ET2018 IoT Forum (Shenzhen Station) and deliver exciting speeches.
Topics include: IoT security chip-level solutions, IoT security, NB-IoT latest applications, IoT + blockchain, IoT + AI, and other exciting topics!
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