1. What are Setup and Hold Times? Answer: Setup time refers to the time during which the data signal must remain stable before the clock edge, while hold time refers to the time during which the data signal must remain stable after the clock edge. If the setup and hold times are not satisfied, the … Read more
1. What Are Setup and Hold Times? Answer: Setup/Hold Time refers to the timing requirements between the input signal and the clock signal for testing chips. Setup time is the time during which the data must remain stable before the rising edge of the clock signal arrives at the flip-flop. The input signal must arrive … Read more
Concept of Logic Analysis The logic analyzer is also a very commonly used instrument, just like the oscilloscope, and is one of the classic instruments for digital design and measurement. When measuring digital circuits, when should an oscilloscope be used? Generally, an oscilloscope can be used when precise parameter information (such as time intervals and … Read more
Tip：Click the above↑ to quickly follow this account For a long time, the logic analyzer has been shrouded in mystery. While most R&D personnel are very familiar with oscilloscopes, they may still be somewhat unfamiliar with logic analyzers. You might guess that it is an expensive, large instrument with a bulky chassis. Right or wrong, … Read more
0x01 Introduction Recently, I purchased a logic analyzer. I had limited exposure to digital signals and inter-chip communication before, but I have been studying these topics intensively over the past few days and now I would like to document my findings for future reference. 0x02 What is a Logic Analyzer Introduction to Logic Analyzers A … Read more
Overview A logic analyzer is an instrument used to analyze the logical relationships in digital systems. It belongs to the category of data domain testing instruments and is a type of bus analyzer, meaning it is based on the concept of buses (multiple lines) and can observe and test data flows across multiple data lines. … Read more
The complexity of ASICs is continuously increasing, and processes are constantly improving. Developing a stable and reusable ASIC chip design within a short time frame, and achieving a successful tape-out on the first attempt, requires a mature ASIC design methodology and development process. This article compares various ASIC design methods using EDA software such as … Read more