Verilog

JTAG Interface Design (5) – JTAG-2

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JTAG Interface Design (5) - JTAG-2

Previously, we discussed the hardware form and basic principles of JTAG. This article uses a JTAG VIP simulation to interpret the waveforms. Referencing SOC Design (4) – Using S Company’s VIP, we first generate an example for JTAG testing: dw_vip_setup -path /home/designware/run_jtag -example jtag_svt/tb_jtag_svt_uvm_basic_sys Enter the simulation directory with cd run_jtag/examples/sverilog/jtag_svt/tb_jtag_svt_uvm_basic_sys, and type in: gmake … Read more

Using DSP48E2 Instantiation

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Using DSP48E2 Instantiation

This article introduces the usage of DSP48E2 instantiation, as follows: DSP48E2 #( // Feature Control Attributes: Data Path Selection .AMULTSEL("A"), // Selects A input to multiplier (A, AD) .A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) .BMULTSEL("B"), // Selects B input to multiplier (AD, B) .B_INPUT("DIRECT"), // Selects B input … Read more

Parametric Structure Design for SPI in FPGA

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Parametric Structure Design for SPI in FPGA

Hello, hero! Welcome to the FPGA technology world. The world is vast, and meeting is fate. You can follow the FPGA technology world to get other interesting resources in the “Adventuring” and “Chivalry” sections, or have a drink and chat together. Today, I bring you the parametric structure design for SPI in FPGA. Without further … Read more

Implementing a Parameterized Priority Multiplexer in Verilog

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Implementing a Parameterized Priority Multiplexer in Verilog

Follow and star our official account for exciting content Source: Online Materials Requirement: In FPGA design, data multiplexers are often required. To achieve parameterized and adjustable designs, we typically need a parameterizable multiplexer, such as M-to-1, where M is an adjustable parameter. If the multiplexer is non-priority, we can design it using a two-dimensional array … Read more

Introduction to ASIC Design Process

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Introduction to ASIC Design Process

The typical ASIC design process can be divided into logical design and physical design. Logical design starts with high-level design specifications and chip architecture. The chip architecture describes high-level functionality, power consumption, and timing (the speed at which the design operates) requirements. This is followed by a description of the design at the register transfer … Read more

UART Serial Communication Principles and Verilog Implementation

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UART Serial Communication Principles and Verilog Implementation

Welcome FPGA engineers to join the official WeChat technical group ClickBlue TextFollow us at FPGA Home – the largest and best FPGA community for pure engineers in China 1.Software and Hardware Platforms Software Platform: 1. Operating System: Windows-8.1 2. Development Suite: ISE14.7 3. Simulation Tool: ModelSim-10.4-SE Hardware Platform: 1. FPGA Model: XC6SLX45-2CSG324 2. USB to … Read more

FPGA Implementation of UART (Including Source Code)

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FPGA Implementation of UART (Including Source Code)

1. What is UART? As one of the three commonly used low-speed buses (UART, SPI, IIC), UART plays an important role in designing various communication interfaces and debugging. UART stands for Universal Asynchronous Receiver/Transmitter, which is mainly used for serial data transmission, and operates in a full-duplex mode. When sending data, it converts parallel data … Read more

FPGA Demystified

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FPGA Demystified

Welcome FPGA engineers to join the official WeChat technical group Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China In 1984, one of the founders of Xilinx, Ross Freeman, a graduate of the University of Michigan, first proposed the concept of Programmable Logic Devices (PLD), … Read more

FPGA Delay Implementation Using Verilog HDL

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FPGA Delay Implementation Using Verilog HDL

Welcome FPGA engineers to join the official WeChat technical group Clickthe blue textto follow us at FPGA Home – the largest and best community for pure FPGA engineers in China This chapter Introduction: Can be started at any time, can be restarted, the delay duration is adjustable, and the unit can be switched (ms/us). The … Read more