This article is part of the “ASIC Design Learning” series by EETOP user: tfpwl_lj. Blog address: http://www.eetop.cn/blog/1638430 1. Introduction For RTL-level ASIC design, there is a vast array of software involved, and the author has not used every single one. There is no need to elaborate further. 2. Tool Introduction RTL Code Rule Check Tools: … Read more
The complexity of ASICs is continuously increasing, and processes are constantly improving. Developing a stable and reusable ASIC chip design within a short time frame, and achieving a successful tape-out on the first attempt, requires a mature ASIC design methodology and development process. This article compares various ASIC design methods using EDA software such as … Read more
Event Details According to incomplete statistics, the number of hardware engineers in China currently exceeds200million. The job gap for hardware engineers is also above60,000.This huge demand for hardware engineers has led many companies’ HR this yearto complain about the difficulty in hiring hardware talents, especially those with practical skills. While you complain about everything rising … Read more
In the process of PCB design and manufacturing, batch chamfering of traces is an important step that helps to enhance the electrical performance and mechanical strength of PCBs, while also facilitating operations during production and assembly.We need to pay attention to some key points of batch chamfering of PCB traces: 01 Purpose of Chamfering • … Read more
Welcome FPGA engineers to join the official WeChat technical group Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China 1 Introduction to FPGA FPGA has a wider range of applications than we usually imagine, due to the greater variety of integrated modules, not just the … Read more
EDA Research Column Integrated circuit EDA tools are not a single tool, but rather a collection of point tools that form a toolchain from front-end design (RTL to gate-level netlist) to back-end design (gate-level netlist to GDS). This includes synthesis, simulation, layout planning, place-and-route, and timing and power analysis optimization. The breakthroughs in EDA tools … Read more
This course series is centered around the RK3588 chip as the core of hardware design, using the latest version of Cadence Allegro Allegro X software to conduct a complete end-to-end project design and simulation of the system’s on-chip resources, interface circuit design, and various commonly used peripheral resources for chip expansion. Integrating the latest software … Read more
This course series uses RK3588 chip as the core hardware design, based on the latest version of Cadence Allegro Allegro X software, to design and simulate the on-chip resources, interface circuits, and various commonly used peripheral resources around the chip. It integrates the latest software features and techniques into daily design, reducing project redundancy and … Read more
Discover Creativity and Fun There are always things worth sharing in life Some say that if during the summer vacation, children are forced to attend training classes they don’t like, it’s not a vacation; it’s a “training class new semester” – all nonsense! Kids who love to play and learn, come on! The Zhongzhi Science … Read more
Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China. FPGA is a programmable chip, thus the design methods for FPGA include both hardware and software design. Hardware includes FPGA chip circuits, memory, input/output interface circuits, … Read more