Overview This article describes the virtualization support of Armv8-A AArch64, including stage 2 page table translations, virtual exceptions, and traps. It introduces some basic hardware-assisted virtualization theories and examples of how some Hypervisors utilize these virtualization features. This text will not discuss how a specific Hypervisor software operates or how to develop a Hypervisor. By … Read more
Related Reading: Differences Between X86 Architecture and Arm Architecture 0. ARMv8 Architecture 1) Basic Concepts of ARMv8 (1) Execution State: The environment in which the processor operates, including register width, supported instruction set, exception model, memory management, and programming model. The ARMv8 architecture defines two execution states: AArch64: 64-bit execution state Provides 31 general-purpose registers … Read more
Click the blue 'Arm Selection' at the top left and select 'Mark as Favorite' 1. Concepts of Exceptions and Interrupts AArch64 exception and interrupt handling In the AArch64 architecture, exceptions and interrupts are one of the key mechanisms to ensure the normal operation of the system. An exception refers to a situation where the system … Read more
Continuing from the previous article, Introduction to MMU in ARMV8-A – Part 4. Page Tables in ARMV8-A ARMV8-A supports three types of page table formats: ARMV8-A AArch64 Long Descriptor Format ARMV7-A Long Descriptor Format, such as the Large Physical Address Extension (LPAE) in the ARM Cortex-A15 processor ARMV7-A Short Descriptor Format Although ARMV8-A uses the … Read more
In 2021, Arm launched the Cortex-A710, the first big core under the armv9 architecture. This year (June 28, 2022), Arm introduced their latest next-generation big core, the Cortex-A715 (also known as Makalu). Following the Cortex-A710, the A715, as the latest big core, supports several enhancements that are largely similar to the ARMv9.0 ISA. More critically, … Read more
The Allwinner H6 chip, launched in 2017, is a high-performance SoC aimed at the OTT, DVB, and IPTV markets. This SoC features a quad-core Cortex-A53 CPU based on the ARM architecture, and its GPU is the ARM Mali T720, supporting OpenGL 3.1, DDR4, and EMMC 5.0. The chip’s performance has improved by 77% compared to … Read more
Prerequisites Prepare the following source packages binutils-2.29 gcc-11.5.0 glibc-2.17 linux-3.10.99 First, build a GCC 5.2, x64 is sufficient. C++11 is required, the default GCC in the repository is 4.4.7 The ARM64 version of glibc 2.17 is required linux-3.10.99 provides header files for glibc 2.17 Set up environment variables export PKG=/soft/pkg export SRC=/dd/gcc-srcexport BUILD=/dd/gcc-buildexport TARGET=aarch64-linux-gnuexport PREFIX=/dd/aarch64-linux-gnu-gcc-11.5.0export … Read more
Consider this: A64 refers to the instruction set architecture, AArch64 is the 64-bit architecture, ARMv8/ARMv9 are also architectures, and TrustZone is a type of security architecture. Confused? What about ARM64? 1. ARMv7/ARMv8/ARMv9 are the true architectures of ARM. The term architecture can be understood as a technical specification, a technical reference, or a design; in … Read more
1. Development of the ARM Architecture The ARM architecture (Advanced RISC Machine) is a microprocessor architecture based on the principles of Reduced Instruction Set Computing (RISC), originally designed and launched by the British Acorn Computer Company in the late 1980s. The evolution of the ARM architecture is as follows: 1.1. Early Development (1980s-1990s) 1985: Acorn … Read more
This article provides a line-by-line explanation of the Armv8-A assembly code sourced from Arm® Development Studio. It focuses on the boot sequence of the AArch64 MPCore processor. This code initializes the system from Exception Level 3 (EL3, typically the Secure Monitor mode) and transitions to Exception Level 1 (EL1, typically the OS mode), during which … Read more