In-Depth Analysis of Linux SMP Technology: From Principles to Practice

In-Depth Analysis of Linux SMP Technology: From Principles to Practice

In-Depth Analysis of Linux SMP Technology: From Principles to Practice 1 Basic Concepts of SMP Symmetric Multiprocessing (SMP) is a computer architecture technology that integrates multiple processors into a single system. Its core feature is that all processors work together in a peer-to-peer manner within a single operating system, sharing a unified memory space and … Read more

An Overview of the BLE Protocol Stack (Part 1)

An Overview of the BLE Protocol Stack (Part 1)

The BLE protocol stack is mainly divided into three layers: the application layer, the host layer, and the controller layer. Many people are likely familiar with this diagram.The application layer mainly consists of various applications with BLE functionality. The host layer provides various protocols and profiles for BLE communication, while also offering API interfaces for … Read more

Chapter 18 of FreeRTOS: Multi-Core Scheduling (SMP Extension)

Chapter 18 of FreeRTOS: Multi-Core Scheduling (SMP Extension)

Table of Contents 1. Overview of SMP Architecture 1.1 Basic Concepts 1.2 FreeRTOS-SMP Features 2. Inter-Core Task Migration Experiment 2.1 Experiment Objectives 2.2 Experiment Steps 2.3 Experiment Result Analysis 3. Protection of Shared Resources in Multi-Core Systems 3.1 Common Issues 3.2 Comparison of Solutions 3.3 Example Code 4. Key API Analysis 4.1 SMP Extension APIs … Read more

Getting Started with FreeRTOS V11.0 SMP in the Era of Embedded Multicore

Getting Started with FreeRTOS V11.0 SMP in the Era of Embedded Multicore

Hello everyone, welcome to <span>LiXin Embedded</span>. FreeRTOS V11.0 provides support for Symmetric Multi-Processing (SMP) on multicore systems. Previously, multicore development often required using various branch versions of FreeRTOS, which was quite cumbersome. Now, V11.0 integrates SMP directly into the mainline, allowing seamless switching between single-core and multicore. Today, we will discuss how to apply this … Read more

Line-by-Line Interpretation of Armv8-A Assembly SMP Boot Code

Line-by-Line Interpretation of Armv8-A Assembly SMP Boot Code

This article provides a line-by-line explanation of the Armv8-A assembly code sourced from ArmĀ® Development Studio. It focuses on the boot sequence of the AArch64 MPCore processor. This code initializes the system from Exception Level 3 (EL3, typically the Secure Monitor mode) and transitions to Exception Level 1 (EL1, typically the OS mode), during which … Read more