In 2021, Arm launched the Cortex-A710, the first big core under the armv9 architecture. This year (June 28, 2022), Arm introduced their latest next-generation big core, the Cortex-A715 (also known as Makalu).
Following the Cortex-A710, the A715, as the latest big core, supports several enhancements that are largely similar to the ARMv9.0 ISA. More critically, all Exception Levels of the A715 only support AArch64 (completely abandoning 32-bit support). The design principles of the A715 are similar to those of previous big cores: improving performance at a higher rate without affecting power and area. In this iteration, the performance focus is on overall improvements, without significantly widening the pipeline or extending its depth. Finally, Arm engineers introduced targeted improvements inspired by earlier Cortex-X designs, such as branch predictors and prefetch enhancements.
Power Efficiency
Compared to the Cortex-A710, the new A715 reportedly offers a 5% performance boost at the same power consumption. Similarly, at the same performance level as the A710, the A715’s power consumption is reduced by 20%. Both comparisons are made in an iso-process context. In other words, Arm claims that the new Cortex-A715 can provide performance comparable to the first-generation Cortex-X1 core. X1 was Arm’s super-large core processor released in 2020.
Overall, it is clear that reducing power consumption is more important in this generation—especially in sustained use cases. This core is somewhat unusual in that the performance boost seems rather modest. Switching between significantly improving performance and greatly reducing power consumption (with much lower performance gains) is not unheard of, but in this particular case, given their 2020 Arm TechCon announcement promising a 30% higher single-core performance than the Cortex-A78, we see around 15% improvement in IPC compared to the A78. It remains unclear why the discrepancy is so large. Nevertheless, the DVFS curve shown below indicates good energy efficiency gains across the performance range.
Microarchitecture
Over time, there have been considerable changes in the technology behind it. The vast majority of changes have occurred in the memory subsystem.
Fetch
Arm spent a significant amount of time perfecting theirprefetcher and branch predictor. This is part of the reason they can maintain relatively small cache sizes. In this iteration, they doubled the capacity of the direction predictor while improving its accuracy. In the previous generation A710, the core could predict two unconditional branches per cycle. Now, in the A710, this feature has been further extended to support conditional branches. In other words, while the A710 could execute one unconditional conditional branch and only one conditional branch, it can now execute two.
Another improvement in the A715 is the introduction of a 3-stage prediction scheme for fast turnaround. Previously, Arm had a fast L0 0 cycle prediction and a slower 2-cycle prediction structure, while in the A715, Arm broke it down into three stages, using a new 1-cycle turnaround intermediate structure, thus reducing the latency of obtaining predictions.
With a higher capacity branch predictor generating higher branch request bandwidth, it may encounter more instances of fetching two separate instruction streams. To accommodate this, the A715 now supports higher instruction cache lookup bandwidth, up to twice the tags per cycle.
64-Bit Only Support
The new Cortex-A715 is a pure AArch64 implementation, which means the design team can eliminate various architectural quirks and inefficiencies brought by 32-bit architecture. Arm states that due to the more regular characteristics of AArch64, the new decoders can not only be designed and optimized more efficiently, but they are also much smaller. In fact, Arm claims that the new decoders are actually “4 times smaller than the decoders in the Cortex-A710 and have matching energy-saving effects,” which is quite remarkable.
With those new decoders, a lot of changes have occurred. First, Arm has adopted an instruction fusion mechanism that directly moves to the instruction cache. Previously, the A710 executed this specifically in the MOP cache. This means that now, all applications can leverage fused instructions at the fetch level (i.e., benefiting from higher effective instruction throughput). Secondly, previously, some instructions could only be handled by specific decoders. Now all decoders can handle all operations.
Due to the smaller size of the AArch64 decoder, Arm added a 5th decoding channel. In other words, the new A715’s fetch/decode bandwidth now matches the A710’s MOP bandwidth, while the instruction cache gains the MOP fusion capability. By moving many advantages of the MOP cache and the newly added decoding channels, Arm claims it can achieve similar performance without the MOP cache. For this reason, it was removed. The removal of the cache also provides some area and power gains, although in terms of performance, a significant design trade-off largely balances each other out.
Memory Subsystem
In the memory subsystem, the Cortex-A715 adds a load response queue. This is a structure that holds published load access rights. Arm has doubled the number of data cache banks. With more banks, there are now more read/write ports, allowing for more concurrent data access. The final change in the A715 is that the L2 TLB entries have now increased by 50%, and Arm states that each entry can now store double the virtual addresses (VA), meaning up to 3 times effective TLB coverage compared to the Cortex-A710 under the right conditions.
Looking ahead, Arm has revealed two new cores for the next two years—Hunter and Chaberton. Software support for Neoverse Demeter and Cortex Hunter & Hayes began rolling out at the end of last year.
