Arm Launches Custom Instructions for Embedded CPUs
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Understanding the Architecture of Arm Cortex-A53 Cache
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This article is authorized and reprinted from the WeChat public account Arm Selected. This article mainly shares the architecture interpretation of A53 cache.
1 A53 uses the classic big-LITTLE architecture
Below is an early classic big-LITTLE architecture diagram.
Figure 1
Figure 2
2 A53's cache configuration
L1 I-Cache
● Configurable: 8KB, 16KB, 32KB, or 64KB
● Cache line: 64 bytes
● 2-way set associative
●
Understanding Embedded System Architecture in One Article
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If you aspire to become a modern embedded systems engineer, you need to determine the system architecture at the beginning of all projects.The system architecture includes two aspects: hardware and software.The hardware part not only determines the complexity and cost of the system but also affects how the subsequent software logic is implemented.Moreover, once determined, it is often difficult to change during the project process.If the architecture needs to be modified, it often leads to significant delays and cost
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