The Rise and Evolution of RISC-V: An Open Source Architecture

The Rise and Evolution of RISC-V: An Open Source Architecture

Recently, Tesla joined the RISC-V Foundation and is considering using free RISC-V designs in its new chips. So far, more than 100 technology companies, including IBM, NXP, Western Digital, NVIDIA, Qualcomm, Samsung, Google, and Huawei, have joined the RISC-V camp. The reason for this phenomenon is partly due to the exorbitant licensing fees of ARM, … Read more

Technical Explanation of Bit Manipulation Instructions in Assembly Language

Technical Explanation of Bit Manipulation Instructions in Assembly Language

1. Instruction Overview Starting from the Intel 80386 processor, the instruction set introduced a powerful set of bit manipulation instructions. These instructions allow programmers to precisely manipulate individual binary bits within operands, including operations such as testing, setting, clearing, complementing, and searching. This greatly enhances the efficiency and convenience of performing bit-level operations (such as … Read more

Summary of Quick Memory Methods for 51 Microcontroller Instructions

Summary of Quick Memory Methods for 51 Microcontroller Instructions

MCS-51 refers to a series of microcontrollers produced by the American company INTEL. This series of microcontrollers includes several varieties, such as 8031, 8051, 8751, 8032, 8052, 8752, etc., among which the 8051 is the earliest and most typical product. When learning about microcontrollers, in addition to understanding the internal functions, memory allocation, and I/O … Read more

Understanding AARCH in Linux: The ARM Architecture Explained

Click the blue WeChat name below the title to quickly follow A few days ago, I saw in a technical document that it said “Linux‘saarch version”, at first I thought it was a mistake, it should be “arch”, did they add an extra “a”? But later I realized I was ignorant, “aarch” is correct. AARCH … Read more

How RISC-V Addresses Hardware Fragmentation Issues

How RISC-V Addresses Hardware Fragmentation Issues

1Introduction In recent years, the rise of RISC-V has drawn attention from the IC industry towards this rapidly developing architecture. However, when it comes to this young architecture, the first things that come to mind are its weak ecosystem and hardware fragmentation. From the very beginning, RISC-V aimed to provide a highly modular and extensible … Read more

Embedded C Language – Computer Architecture and CPU Operation Principles

Embedded C Language - Computer Architecture and CPU Operation Principles

The core of computer architecture lies inthe instruction set which defines “what to do,”the microarchitecture determines “how to do it,”the packaging and bus decide “how to connect,”the memory hierarchy determines “how fast to access data,”and parallelism and dedicated units determine “how much can be done.” From the Turing machine to modern SoCs, all complex computations … Read more

Characteristics of the RISC-V Instruction Set

Characteristics of the RISC-V Instruction Set

1. Characteristics of the RISC-V Instruction Set(1) Open Source Nature and Community-Driven:The instruction set architecture is open source,adopting a permissive BSD license, with characteristics of the BSD license introduced in(Hard Ten Huashan Development Board Series (7): Open Source Innovation, Closed Source Delivery). Companies can use it freely and at no cost, and they are also … Read more

RISC-V Instruction Set Manual Volume I | 3. RV32E and RV64E Base Integer Instruction Set, Version 2.0

RISC-V Instruction Set Manual Volume I | 3. RV32E and RV64E Base Integer Instruction Set, Version 2.0

From https://github.com/riscv/riscv-isa-manualTranslated by Visual Studio Code CopilotAI Engine: Claude Sonnet 4 3. RV32E and RV64E Base Integer Instruction Set, Version 2.0 This chapter describes the proposal for the RV32E and RV64E base integer instruction sets, designed specifically for microcontrollers in embedded systems. RV32E and RV64E are simplified versions of RV32I and RV64I, respectively: the only … Read more

RISC-V DSP New Instruction Set and DSA Architecture Drive Innovations in Wireless Communication Performance!

RISC-V DSP New Instruction Set and DSA Architecture Drive Innovations in Wireless Communication Performance!

In increasingly complex wireless communication systems, achieving high performance and low power consumption in digital signal processing (DSP) under process-constrained environments has become a significant challenge for chip architects. At the fifth RISC-V China Summit’s Frontier Innovation Technology Sub-Forum, Li Gaoshan, a senior expert from ChipRise Technology and a top talent from China Mobile, delivered … Read more

Abandoning MIPS, 100% Self-Developed: Loongson’s Right Move!

Abandoning MIPS, 100% Self-Developed: Loongson's Right Move!

Recently, there has been news in the chip industry: the long-established semiconductor IP company MIPS has been sold again, this time to the chip foundry giant GlobalFoundries. Upon hearing the news, many people lamented: MIPS’s 40-year history of ups and downs is like a “journey of wandering”—from being acquired by Imagination, to being split and … Read more