TAP controller The TAP controller is a finite state machine that transitions states based on the TMS signal at the rising edge of TCK, generating control signals to operate the JTAG circuit. The state transition diagram of the TAP controller is shown below: Each state is described as follows: Test-Logic-Reset: The test logic is disabled, … Read more
The JTAG online read/write board for inverter air conditioners, G-Matrik TMS320F28035, requires the installation of a QFP80 programming seat on the programmer. The RT809H programmer is suitable for this purpose. For online read/write, please enter the following in the software: TMS320F28035 #ISP Be careful not to select the wrong option; for online read/write, choose the … Read more
1. What is a BSDL File? In the last article, we introduced the basics of JTAG boundary scan, today we will look at a file that is essential for boundary scan testing, the BSDL file. BSDL, Boundary Scan Description Language is an abbreviation for Boundary Scan Description Language, a subset of VHDL that conforms to … Read more
While reviewing the resource utilization report of the project, we discovered a special underlying hardwareBSCAN, as shown in 1. Let’s understand its uses and applications. Figure1.The resource report shows the number and usage ofBSCAN. Figure2.Finding the path ofBSCANin the code Figure3.Locating the project call to the underlying module Figure4.Finding the location and interconnections ofFPGAunderlyingBSCAN. Figure5.Finding … Read more
This article is authored by AMD engineer Longley Zhang. In AMD SoC devices (AMD Zynq™ 7000 SoC, AMD Zynq UltraScale+™ MPSoC, AMD Versal™ Adaptive SoC), a common boot method is to load an image from external memory (QSPI Flash, eMMC, etc.) to boot directly into Linux. However, during board debugging, it is often necessary to … Read more
Following the previous article, we learned about the erase, write, and read functions of FLASH, but there is still a lack of understanding regarding the relationship with JTAG. This article supplements the JTAG part. First, let’s take a look at the hierarchical structure of JTAG programming FLASH, as shown in the figure below: The physical … Read more
Previously, we discussed the hardware form and basic principles of JTAG. This article uses a JTAG VIP simulation to interpret the waveforms. Referencing SOC Design (4) – Using S Company’s VIP, we first generate an example for JTAG testing: dw_vip_setup -path /home/designware/run_jtag -example jtag_svt/tb_jtag_svt_uvm_basic_sys Enter the simulation directory with cd run_jtag/examples/sverilog/jtag_svt/tb_jtag_svt_uvm_basic_sys, and type in: gmake … Read more
Developing and debugging embedded systems is a complex task that requires powerful tools and interfaces to ensure the correctness of hardware and software. In this field, JTAG (Joint Test Action Group) and SWD (Serial Wire Debug) are two commonly used debugging interface standards that play a crucial role in embedded system development. This article will … Read more
Today, a customer visited us. Their company used S3C2440 to create a product and encountered some issues: 1. Sometimes the program can be burned to NOR Flash using H-JTAG, and sometimes it cannot; when it fails to burn, H-JTAG shows an error message “Unable to load driver”. 2. When it is lucky enough to burn … Read more
Question: JTAG has 5 ports, why is Trst an optional reset port? Question: If JTAG only retains 4 ports, how do we reset without Trst? Answer: The first question is simple; Trst can be replaced with Tms. What about the second question? Feel free to discuss in our knowledge community. Question: After adding mbist and … Read more