UVM

SoC Verification Process and Methods

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SoC Verification Process and Methods

Source: EETOP Original Author: EETOP Compilation We need increasingly complex chips and SoCs for all new applications using the latest technologies such as artificial intelligence. For example, Apple’s 5nm SoC A14, which contains 11.8 billion transistors, features a 6-core CPU, a 4-core GPU, and a 16-core NPU engine, capable of performing 11 trillion operations per … Read more

JTAG Interface Design (5) – JTAG-2

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JTAG Interface Design (5) - JTAG-2

Previously, we discussed the hardware form and basic principles of JTAG. This article uses a JTAG VIP simulation to interpret the waveforms. Referencing SOC Design (4) – Using S Company’s VIP, we first generate an example for JTAG testing: dw_vip_setup -path /home/designware/run_jtag -example jtag_svt/tb_jtag_svt_uvm_basic_sys Enter the simulation directory with cd run_jtag/examples/sverilog/jtag_svt/tb_jtag_svt_uvm_basic_sys, and type in: gmake … Read more