As the scale and functionality of SOC chips continue to expand dramatically, SOC verification can account for more than 60% of the entire project, making verification a bottleneck in the development of SOC chips. Insufficient chip verification can lead to severe losses, such as re-taping, wasting time and capital, and in severe cases, depletion of … Read more
Recently, I spent some time organizing the verification of the SPI module in the USI module of the WUJIAN100 project. Here, I would like to share some of my thoughts and methods. Basic Introduction to the Design Functionality of the USI Module USI (Unified Serial Interface) is a combined module that includes UART, SPI, and … Read more
Source: EETOP Original Author: EETOP Compilation We need increasingly complex chips and SoCs for all new applications using the latest technologies such as artificial intelligence. For example, Apple’s 5nm SoC A14, which contains 11.8 billion transistors, features a 6-core CPU, a 4-core GPU, and a 16-core NPU engine, capable of performing 11 trillion operations per … Read more
Previously, we discussed the hardware form and basic principles of JTAG. This article uses a JTAG VIP simulation to interpret the waveforms. Referencing SOC Design (4) – Using S Company’s VIP, we first generate an example for JTAG testing: dw_vip_setup -path /home/designware/run_jtag -example jtag_svt/tb_jtag_svt_uvm_basic_sys Enter the simulation directory with cd run_jtag/examples/sverilog/jtag_svt/tb_jtag_svt_uvm_basic_sys, and type in: gmake … Read more