Introduction When you first rewrite Python’s performance bottlenecks in Rust, eagerly anticipating performance improvements, only to find that performance analysis shows 60% of the time wasted on hidden data copies—this experience can be both amusing and frustrating. In fact, when passing large-scale data between Python and Rust, boundary handling is more important than kernel algorithms. … Read more
A Brief Summary of Core Differences FIFO: A hardware buffer queue that primarily addresses the minor, short-term mismatches between MCU response speed and SPI communication speed, aiming to reduce the number of interrupts and improve the efficiency of each interrupt. PDMA: A data transfer engine that mainly solves the problem of freeing the CPU during … Read more
1. Data Transfer Instructions MOV: Transfer word or byte ->>>>>>>>>>>>>>>>>>>>>>>>>>>> CHUAN means transfer MOVSX: Sign extend first, then transfer ->>>>>>>>>>>>>>>>>>>>>> CHUANFHR means transfer sign to any register MOVZX: Zero extend first, then transfer ->>>>>>>>>>>>>>>>>>>>>> CHUANLR means zero extend any register then transfer PUSH: Push word onto stack ->>>>>>>>>>>>>>>>>>>>>> RUZH means push onto stack POP: Pop … Read more
FreeRTOS provides various communication mechanisms for inter-task communication, including queues, semaphores, mutexes, event groups, and task notifications. Below is a detailed introduction to queues.Queues Queues support asynchronous data transfer between tasks and between tasks and ISRs. They can transfer any type of data and support multiple tasks sending data to the same queue, as well … Read more
This article delves into innovative methods for on-chip data transfer, exploring how embedded engineers can strategically design FPGA systems to alleviate the memory wall issue and fully unleash the potential of these powerful devices. For embedded engineers, Field Programmable Gate Arrays (FPGAs) represent a powerful paradigm for accelerating compute-intensive applications. Their inherent parallelism and reconfigurability … Read more
We will provide a detailed introduction to the very important DDR bus. This is a comprehensive introduction from basic concepts to technical details. 1.What is the DDR bus? The DDR bus is an electronic channel used in computers to transfer data, addresses, and control commands between the memory controller (usually located within the CPU) and … Read more
1 Introduction Direct Memory Access (DMA) is a component used by the CPU to transfer data from one address space to another without CPU intervention. Once the data transfer is complete, the CPU is notified to process the data. Therefore, using DMA can free up CPU resources during large data transfers. Typical DMA data transfer … Read more
When performing ADC acquisition on STM32, the difference in time efficiency between using software (interrupt or polling) to transfer data and using DMA to transfer data is very significant. This difference is mainly reflected in CPU time consumption and system responsiveness, rather than the time taken for a single sampling conversion itself. For example, consider … Read more
FlexRay is a brand new bus and communication system, with a maximum data transfer rate of up to 10 MBit/s for each channel, making FlexRay a very high-speed communication system. The data transfer speed of FlexRay is significantly faster than the previously widely used data buses in the body, drive, and chassis areas (such as … Read more
Introduction In the SATA protocol, the essence of data transmission is the interaction of FIS (Frame Information Structure). Different FIS types are responsible for different aspects: some are for “notification”, some for “context configuration”, and others for “actual data transfer”. If we consider SATA as a highway, then these FIS are like traffic lights, road … Read more