Powerful JTAG Boundary Scan 5 – FPGA Boundary Scan Applications

Previous article, introduced the JTAG boundary scan application based on STM32F103, demonstrated the application of TopJTAG Probe software, and the basic functions of boundary scan. This article introduces the boundary scan application based on Xilinx FPGA, which is almost the same.

1. Obtain the Chip’s BSDL File

The method of obtaining the BSDL file for FPGA can refer to the previous article: Obtaining BSDL Files.
Taking the Xilinx Kintex-7 series FPGA XC7K325T as an example, it can be obtained from the BSDL Library website (www.bsdl.info ) or from the installation directory of ISE and Vivado,
D:\Program\Xilinx\14.7\ISE_DS\ISE\kintex7\data
D:\Program\Xilinx\Vivado\Vivado\2018.3\ids_lite\ISE\kintex7\data

2. Hardware Connection

First, prepare the following hardware:

  • JTAG debugger, such as JLink V9 standard version

  • An FPGA board, such as Xilinx XC7K325T

Powerful JTAG Boundary Scan 5 - FPGA Boundary Scan Applications

The JTAG interface of Xilinx and the JLink JTAG interface have different pin sequences, so separate dupont wires are needed to connect TCK, TMS, TDI, TDO, and VREF, GND signals.
Powerful JTAG Boundary Scan 5 - FPGA Boundary Scan Applications

3. Boundary Scan Testing

Open TopJTAG to create a new project, select JTAG device as JLink
Powerful JTAG Boundary Scan 5 - FPGA Boundary Scan Applications
If the connection is normal, the IDCODE of the currently connected chip will be displayed
Powerful JTAG Boundary Scan 5 - FPGA Boundary Scan Applications
Specify the BSDL file path and perform IDCODE verification.
Powerful JTAG Boundary Scan 5 - FPGA Boundary Scan Applications
The initial state is stop state,
Powerful JTAG Boundary Scan 5 - FPGA Boundary Scan Applications
The initial default is Sample state, click the RUN button to see the real-time status of all pins, black indicates power pins, black indicates high level, blue indicates low level. Flashing indicates that the current state is high-low level flip state.
Powerful JTAG Boundary Scan 5 - FPGA Boundary Scan Applications
In the left Pins window or the right chip view, select a chip pin, right-click, and you can choose to add it to the Watch window or Waveform window
Powerful JTAG Boundary Scan 5 - FPGA Boundary Scan Applications
The Watch window can see the real-time status of the pins and can count the number of level flips, the Waveform window can display real-time waveforms.
Powerful JTAG Boundary Scan 5 - FPGA Boundary Scan Applications
The Waveform supports basic operations such as zooming in, zooming out, and pausing.
Powerful JTAG Boundary Scan 5 - FPGA Boundary Scan Applications
In the Pins window, after selecting a pin and right-clicking, you can name it, output high, low level, or high impedance state.
Powerful JTAG Boundary Scan 5 - FPGA Boundary Scan Applications
Support batch control of level status after multi-selection
Powerful JTAG Boundary Scan 5 - FPGA Boundary Scan Applications
Support batch addition to the Waveform window after multi-selection
Powerful JTAG Boundary Scan 5 - FPGA Boundary Scan Applications

4. Summary

Unlike microcontrollers, most FPGA chips are BGA packaged, with pin counts ranging from 200 to 1000, which means that multi-layer PCBs are needed for hardware design. The dense pins and inner layer routing of PCBs make troubleshooting increasingly difficult. Through boundary scan, fault points can be quickly and easily identified, greatly improving efficiency during product development, production, and testing phases.

Powerful JTAG Boundary Scan 5 - FPGA Boundary Scan Applications

More Selections

  • Powerful JTAG Boundary Scan 4 – STM32 Boundary Scan Applications

  • Powerful JTAG Boundary Scan 3 – Common Boundary Scan Testing Software

  • Powerful JTAG Boundary Scan 2 – BSDL Files

  • Powerful JTAG Boundary Scan 1 – Basic Principles

  • China Mobile Wan Kou Tian Gong Development Board Trial Review

  • Download Xilinx FPGA Programs with JLink and OpenOCD

  • Four Methods to Obtain Xilinx FPGA Chip IDCODE (Supports Any FPGA Model)

  • What is Amateur Radio?

  • Xilinx FPGA Multiboot Design and Implementation (Spartan-6 and Kintex-7 Examples)

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