Understanding JTAG Boundary Scan Technology

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Introduction:

Engineers engaged in hardware, embedded systems, or chip-related fields are likely familiar with JTAG. JTAG primarily has three main uses:

1. Testing and Diagnosis: Initially, the main purpose of JTAG was for testing and diagnosing integrated circuits, used to detect and repair defects in the chip manufacturing process.
2. Device Programming: Through JTAG, firmware, configuration files, or programs can be loaded onto chips using a programmer.
3. Hardware Debugging: With JTAG, engineers can connect debuggers or emulators to monitor the chip’s status, register values in real-time, and even perform step-by-step execution.

What is the standard definition of JTAG? It was proposed by the Joint Test Action Group and later standardized with IEEE as IEEE 1149.1. The full name is IEEE Standard for Test Access Port and Boundary-Scan Architecture. Thus, JTAG originated from a joint working group of multiple companies aiming to create a standard interface for semiconductor testing and debugging. This standard later evolved into IEEE 1149.1 and became a widely used interface standard.

This article aims to share the core technology of the JTAG standard interface—Boundary Scan Chain. The basic principle is quite simple, and this technology can easily be applied to your own FPGA project, chip testing, or even board-level testing, providing users with a standardized systematic debugging or testing method. Interested readers can follow our public account “FPGA Application Development” for future articles where I will open-source the actual project logic source code based on JTAG’s boundary scan chain.

Meaning of Boundary Scan

Before understanding the basic principles of JTAG, we first need to understand the meaning of boundary scan.

Boundary scan can extend the scanning path to the board level or system level. All information exchanged with the outside (including instructions, test data, and test results) for devices designed based on boundary scan is communicated serially. This allows instructions and related test data to be sent serially to the device, and the execution results of the test instructions to be read out from the device serially. To achieve this functionality, boundary scan technology includes a scan chain composed of boundary scan register units connected to the device pins, allowing control and observation of the device’s boundary signals through scanning test principles, which is the meaning of boundary scan.

Note:

Taking “chip” as an example, how the boundary scan chain controls the chip’s inputs and outputs:

1. If you need to capture the output of a specific pin or internal logic state of the chip: First, the output on that pin needs to be loaded into the boundary scan chain’s register unit, then output through TDO, allowing us to obtain the corresponding output signal from TDO. (Capture)

2. If you want to load a specific signal onto a pin of the chip, you first need to shift the desired signal into the boundary scan chain’s register unit connected to the corresponding pin through TDI, and then load the value of that register unit onto the respective chip pin. (Shift, Update)

JTAG Standard Circuit Structure

Note:

• 4 dedicated test pins (TCK, TMS, TDI, TDO), collectively referred to as the Test Access Port (TAP).
• 1 TAP controller (state machine) with input TCK and TMS, which generates the clock and control signals required for the IR and DR registers (such as shift, capture, and update operations).
• 1 n-bit (>=2) instruction register (IR), which stores the current instruction (including Bypass, Identify, Boundary-Scan, and other options).
• The data register includes Bypass, Identify, Boundary-Scan, and other optional registers.
• The boundary scan logic is controlled by the TAP Controller, DR, and IR working together.

Common Instructions

Different instructions constrain the various operations of the boundary scan logic. JTAG instructions appear in binary encoded form. Instruction data is serially shifted into the instruction register from the TDI port on the rising edge of TCK when the TAP controller is in Shift-IR state. Some instructions must be implemented, while others are optional.

Instruction Type	Name	Selected Register	Description
Mandatory	BYPASS	Bypass
EXTEST (External Test)	Boundary Scan	External tests, such as interconnect testing between chip pins.
SAMPLE (Sampling)	Boundary Scan	Sampling, for example, capturing data from the device pins.
PRELOAD (Preload)	Boundary Scan	Preload, for example, preloading known test data into output pin units.
Optional	INTEST (Internal Test)	Boundary Scan	Internal tests, allowing the boundary scan register to serve as the device’s input and output for static testing of the core logic.
IDENTIFY (Device Identification)	Device Identification	Places a 32-bit device identification register on the TDI and TDO scan chain to store the manufacturer’s details, version type, and other information.
RUNBIST (Built-In Self-Test)	Designated Test Register	When the TAP controller is in run-test/idle state, the chip can perform self-tests and place the test results (pass/fail) in designated registers.

Bypass: The instruction is assigned a code of all 1s. At this time, the scan chain consists only of a 1-bit Bypass register. The BYPASS instruction scans data from TDI to TDO through a 1-bit bypass register, rather than through the entire boundary scan chain. This bypasses chips that do not require testing, as shown in the diagram where the scan chain bypasses chip 1 to enter chips 2 and 3.

Sample and Preload: The Sample instruction is used to capture signals related to sampling points (i.e., parallel input terminals in boundary scan design) into the boundary scan register without affecting the normal operation of the core logic. The Preload and Sample instructions function similarly, except that the data loaded into the boundary scan register is known or predetermined by the operator. For instance, during a specific test, a particular data can be preloaded to ensure the boundary scan register outputs a completely safe state.

Extest: Primarily used to test connections between ICs or logic circuits outside the boundary scan design. It locks data from the boundary scan register (BSR) into the data register to stimulate the tested connections or external logic circuits, while capturing the responses of the tested connections or external logic circuits under that stimulus. (Before executing the external test instruction, a preload instruction is needed to load the stimulus vector into BSR. After completing the external test instruction, a shift instruction should be used to extract the test results for inspection.)

Boundary Scan Chain

The boundary scan register can be selected by Extest, Sample, Preload, and Intest instructions.

Each boundary scan unit is connected in a “shift” mode, where the output of the previous scan unit connects to the input of the next scan unit, forming a “shift” register chain.

Boundary Scan Register

Basic General Boundary Scan Unit

TAP Controller and State Machine:

From the first diagram in this article, TMS and TCK connect to a TAP controller, which generates various control signals, including dedicated signals for IR (ClockIR, ShiftIR, UpdateIR) and signals common to all data registers (ClockDR, ShiftDR, UpdateDR). Additionally, there are general selection (Select), reset (Reset), and enable (Enable) signals.

The next diagram shows the state table of the TAP controller. The values on the state transition arcs represent the TMS values. State transitions occur on the rising edge of TCK, and output values change on the falling edge of TCK.

TAP Controller State Machine

Capture-DR:

On the rising edge of TCK, the signal will be “captured” into the corresponding data register unit. If TMS is “0” (triggered by the rising edge of TCK), it enters the Shift-DR state; if TMS is “1”, it enters the Exit1-DR state.

Shift-DR:

Each clock cycle, the previously captured data is sequentially passed through the data register scan chain and finally output serially through TDO. If TMS is “0” (triggered by the rising edge of TCK), it remains in the Shift-DR state; if TMS is “1”, it transitions to Exit1-DR state.

Update-DR:

In the Update-DR state, the data in the data register will be loaded to the corresponding control ports. If TMS is “0”, the TAP Controller returns to the Run-Test/Idle state; if TMS is “1”, the TAP Controller enters the Select-DR-Scan state.

Note:

Where the captured data comes from and where it shifts to can be controlled based on actual applications. For example, if your scan chain logic is mainly used for testing internal logic circuits of the chip, the captured data mainly comes from the internal logic circuit. If used for testing chip pins, signals need to be sent to a specific input pin of the chip through TDI, thus capturing the signal input from TDI. The same applies to updating data.

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