Who Moved My JTAG Port?

In the process of FPGA development and learning, a key step is downloading to the board. Achieving hardware “hard presence” is very important, and generally, the JTAG port is more commonly used. Therefore, I believe that some experts must have encountered issues with the JTAG port becoming unresponsive or damaged and unable to be used.

Recently, I encountered such a situation where the JTAG port of the FPGA suddenly could not download programs, and this is not the first time it has happened. Previously, when working on a project, a similar issue occurred. It worked fine one day, and the next day it didn’t, which was quite frustrating.

As a result, I tried many solutions. Initially, I didn’t consider that the JTAG port might be broken, so I replaced the USB blaster, but there was no response at all. Could it really be that the JTAG port is broken? Later, I consulted relevant materials to clarify the essence of the problem…

Below are some of my findings, shared for your reference, and I hope we can exchange and learn together.

Based on the materials I consulted and my practical experience, when using the JTAG download interface, please do not connect or disconnect it while powered, as this can damage the JTAG signal pins of the FPGA chip. So how can we confirm if the JTAG port is damaged?

First, you need to rule out some basic factors: one is whether the connections are matched, as many devices correspond to many interfaces, and it is necessary to match them correctly under actual conditions; the second is to rule out issues with the download cable. If the download cable is faulty, you can try using multiple cables to eliminate this type of issue. If you still cannot access the FPGA’s JTAG port, it is very likely that the JTAG port of your FPGA chip is damaged. At this point, please use a multimeter to check TCK, TMS, TDO, and TDI to see if they are shorted to GND. If any signal is shorted to ground, it indicates that the JTAG signal pins are damaged.

As for what JTAG is, let’s discuss it here. JTAG stands for Joint Test Action Group.

JTAG is an IEEE standard used to solve board-level issues and was born in the 1980s. Today, JTAG is used for programming, debugging, and probing ports. Of course, its original use was boundary testing.

1. Boundary Testing

For example, if you have two chips connected by many wires, how do you ensure that the connections between these wires are okay? You use JTAG, which can control all the IC pins; this is called chip boundary testing.

2. JTAG Pins

JTAG has developed to now and typically has four pins: TDI, TDO, TMS, TCK, and there is also a reset pin TRST.

The JTAG pins on the chip are actually dedicated:

TDI: Test Data Input, data is input to the JTAG port through TDI.
TDO: Test Data Output, data is output from the JTAG port through TDO.
TMS: Test Mode Select, used to set the JTAG port to a specific test mode.
TCK: Test Clock Input.
TRST: Test Reset.

CPU and FPGA manufacturers allow JTAG for port debugging; FPGA manufacturers allow configuration of the FPGA through JTAG, using JTAG signals into the FPGA core.

3. How JTAG Works

The PC controls JTAG: connect the JTAG cable to the PC’s printer port, USB, or network port. The simplest connection is to the printer port.

TMS: Inside each chip that contains JTAG, there will be a JTAG TAP controller. The TAP controller is a state machine with 16 states, and TMS is the control signal for this. When TMS connects all chips together, the TAP states of all chips transition consistently.

Below is a schematic diagram of the TAP controller:

Changing the value of TMS will change the state. If it maintains a high level for 5 cycles, it will return to test-logic-reset, usually used to synchronize the TAP controller; the two most important states are Shift-DR and Shift-IR, both of which connect TDI and TDO.

IR: Instruction Register, you can write values to this register to notify JTAG to perform a task. Each TAP has only one IR register, and its length is fixed.

DR: TAP can have multiple DR registers, similar to the IR register, where each IR value selects a different DR register.

4. Questions Related to the JTAG Chain

Calculating the Number of ICs in the JTAG Chain:

An important application is when the IR value is all ones, indicating the BYPASS command. In BYPASS mode, the DR register in the TAP controller is always a single bit, from input TDI to output TDO, usually one cycle, doing nothing.

You can use BYPASS mode to calculate the number of ICs. If the delay of the TDI-TDO chain for each IC is one clock, we can send some data and detect how long it is delayed, which can then be used to deduce the number of ICs in the JTAG chain.

Obtaining the Device ID in the JTAG Chain:

Most JTAG ICs support the IDCODE command. In the IDCODE command, the DR register will load a 32-bit value representing the device ID. Unlike the BYPASS instruction, there is no standard for the IR value in IDCODE mode. However, each time the TAP controller transitions to the Test-Logic-Reset state, it will enter IDCODE mode and load the IDCODE into the DR.

5. Boundary Scan

When the TAP controller enters boundary scan mode, the DR chain can traverse each IO block or read or intercept each pin. Using JTAG on an FPGA, you can know the state of each pin while the FPGA is running. You can use the JTAG command SAMPLE; of course, different ICs may vary.

If the JTAG port is already damaged, then you can only “mourn and accept it,” but do not just dwell on sadness. The most important thing is to analyze the reasons behind it; the same principle applies to other matters. So let’s analyze: during usage, we may often connect and disconnect the JTAG download port for convenience. In most cases, this will not cause issues. However, there is still a small chance of encountering the following problems due to hot-swapping, resulting in static electricity and surges at the JTAG port, ultimately leading to the breakdown of the FPGA pins.

At this point, some may suspect whether it is due to a counterfeit USB Blaster or ByteBlasterII design simplification that removed protective circuits. However, feedback from many practical situations has proven that even the original USB Blaster can encounter the same issues. Others have raised doubts about whether ALTERA’s low-end chips lack diode clamp protection circuits to reduce costs. These doubts do not address the essence of the problem. The most important thing is to standardize operations and minimize hardware devices and interfaces from failing prematurely due to improper handling. Now, let’s focus on how to standardize the use of the JTAG download port.

Power-On Operation Procedure:

Under the premise that the FPGA development board and related devices are powered off, connect the JTAG download cable;
Connect the USB Blaster or ByteBlasterII cable;
Power on the FPGA development board.

Power-Off Operation Procedure:

Turn off the power to the FPGA development board and related devices;
Disconnect the USB Blaster or ByteBlasterII cable;
Remove the JTAG download cable and store it in a suitable place.

Although the above steps may seem cumbersome, and we may sometimes overlook them during use, to ensure the chip is not damaged, it is recommended to follow these steps properly.

After testing, the issue I encountered was a short circuit between TCK and GND. Although the probability of this happening is not very high, to use hardware devices more reasonably and for a longer time, I still recommend that everyone do not mind the complexity during practical operations. Think from a different perspective; “more practice” is beneficial to yourself.

Lastly, let me reiterate that regarding the use of the JTAG download port, it is best not to perform hot-swapping while powered. At least this can prolong the life of the JTAG port. After all, a long-lasting companionship is quite nice; don’t wait until you’ve lost it to feel regret.

Source: FPGA Technology Jianghu

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1. Boundary Testing

2. JTAG Pins

3. How JTAG Works

4. Questions Related to the JTAG Chain

5. Boundary Scan

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