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This article mainly discussesClock Resources in Xilinx FPGA: Introduction to DCM, PLL, MMCM, and CMT
The most common complete set includes: DCM, PLL, MMCM, which are usually encapsulated in a larger module called CMT.
DCM: Digital Clock Manager – the earliest and most basic module
PLL: Phase-Locked Loop – an analog/mixed-signal module, more advanced than DCM
MMCM: Mixed-Mode Clock Manager – an enhanced version of PLL, with the most comprehensive functionality
CMT: Clock Management Tile – a physical location containing MMCM/PLL and auxiliary resources
DCM – Digital Clock Manager
DCM is an earlier generation clock management module from Xilinx, primarily found in older devices such as Virtex-4 and Spartan-6.
Core principle: Based on a digital delay-locked loop. It aligns the clock phase using an adjustable digital delay line to eliminate clock offset.
Main functions: Clock offset removal: Eliminates delays caused by the FPGA’s internal global clock network, ensuring clock edges are precisely aligned with external input clocks. This is its core function. Frequency synthesis: Can generate clock frequencies that are multiples or fractions of the input clock, but with less flexibility and range than PLL/MMCM. Phase adjustment: Can produce clocks with fixed phase offsets (e.g., 0°, 90°, 180°, 270°). Dynamic reconfiguration: Can adjust phase and frequency within limits at runtime.
Characteristics: Purely digital implementation, relatively weak noise immunity, limited frequency synthesis capability, and average jitter performance. It has gradually been phased out in modern designs.
PLL – Phase-Locked Loop & MMCM – Mixed-Mode Clock Manager
Starting from the Virtex-5 and 7 series and later devices, more advanced PLL and MMCM have become the absolute mainstream. MMCM can be viewed as a superset or enhanced version of PLL.
PLL – Phase-Locked Loop
Core principle: Based on analog/mixed-signal circuits. It uses components like voltage-controlled oscillators and charge pumps to generate clocks.
Main functions: Frequency synthesis: Powerful multiplication and division capabilities, can produce a wider range and more precise output frequencies. Jitter filtering: The analog loop itself has low-pass filtering characteristics, effectively filtering jitter from the input clock, providing a cleaner and more stable output clock. Clock deskew: Similar to DCM, but with better performance.
Characteristics: Mixed-signal implementation, jitter performance superior to DCM, frequency synthesis capability stronger than DCM.
MMCM – Mixed-Mode Clock Manager
MMCM is developed based on PLL and is currently the most powerful and commonly used clock management module in Xilinx (AMD) FPGAs.
Core principle: Also based on analog PLL, but adds digital functions and finer dividers.
Enhanced features compared to PLL: Finer phase adjustment: MMCM has a phase offset fine-tuning function, allowing dynamic and precise adjustment of the output clock phase in very small steps (e.g., 1/56 of the VCO period). This is crucial for timing alignment in source-synchronous interfaces (e.g., DDR). More flexible duty cycle adjustment: Can precisely control the duty cycle of the output clock (the ratio of high-level time to period). Wider output frequency range: Typically supports a broader range of input and output frequencies.
Characteristics: The most comprehensive clock management unit. MMCM is the preferred and commonly used choice in almost all designs of 7 series and newer devices. Unless resources are exhausted, weaker PLL or DCM will not be chosen.
Simple comparison: PLL vs MMCM
MMCM ≈ PLL + Fine Phase Adjustment + Duty Cycle Control
In the latest devices like Ultrascale+, official documentation usually only mentions MMCM, as it fully encompasses the functionality of PLL.
CMT – Clock Management Tile
CMT does not refer to a specific functional module, but rather a physical resource block.
In the layout of FPGA chips, clock resources are not randomly scattered. Manufacturers package related clock management units (like MMCM/PLL) and clock buffers (BUFG, BUFH, BUFR, etc.) together and place them in specific vertical columns on the chip. This “package” is called a CMT.
For example, in 7 series FPGAs, a CMT contains: 1 MMCM, 2 PLLs.
The layout of CMT determines the distribution of clock resources within the FPGA. When you use an MMCM, the PLL resources within the same CMT cannot be used (as they share some input paths). Understanding CMT helps in planning clock resources in large designs to avoid clock routing congestion.
Summary and Comparison
Design Selection Recommendations
Modern designs (7 series and later): Unconditionally prefer MMCM. It provides the most powerful functionality and best performance, meeting almost all clock requirements, including high-speed serial communication, memory interfaces, and other scenarios with extremely stringent timing requirements.
When resources are limited: If a design requires many clock management units, after exhausting MMCM, consider using the PLL within the same CMT for some auxiliary clock generation tasks that do not have high performance requirements.
Maintaining old projects: You will only encounter DCM when maintaining projects based on older devices like Spartan-6. It should not be used in new designs.
In summary, MMCM is the most powerful clock management core in modern FPGA designs, while CMT is the physical home containing these cores. PLL is a functional subset of MMCM, and DCM is an obsolete technology.
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