In daily work, many people often ask about the difference between CDR solutions and DSP solutions, especially in the context of QSFP56 200G SR4 and QSFP-DD 400G SR8 optical modules and their corresponding AOC series products. This article will detail the differences in functionality, principles, technical characteristics, application scenarios, and implementation methods of the two … Read more
1. Why Use Serdes 　　 Traditional source-synchronous transmission separates clock and data. There are no issues at lower rates (<1000M). As the rates increase, this becomes problematic 　　Due to inconsistent delay and jitter in transmission lines, the receiver cannot sample data correctly, resulting in misaligned eye diagrams. This leads to the idea of recovering the … Read more
Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China 1. Why Use Serdes Traditional source synchronous transmission separates clock and data. This works fine at lower rates (<1000M). However, this becomes problematic at higher rates. … Read more
Many engineers who started learning with the 51 microcontroller might feel a bit confused by this question. How can a parallel interface, which can send a large amount of parallel data, be slower than a serial interface? The 51 microcontroller also has a parallel port, which is used for driving LCD screens and connecting external … Read more