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In-Depth Study of Xilinx High-Speed Transceivers Serdes

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In-Depth Study of Xilinx High-Speed Transceivers Serdes

1. Why Use Serdes 　　 Traditional source-synchronous transmission separates clock and data. There are no issues at lower rates (<1000M). As the rates increase, this becomes problematic 　　Due to inconsistent delay and jitter in transmission lines, the receiver cannot sample data correctly, resulting in misaligned eye diagrams. This leads to the idea of recovering the … Read more

In-Depth Study of Xilinx High-Speed Transceivers (Serdes)

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In-Depth Study of Xilinx High-Speed Transceivers (Serdes)

Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China 1. Why Use Serdes Traditional source synchronous transmission separates clock and data. This works fine at lower rates (<1000M). However, this becomes problematic at higher rates. … Read more