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8-1 A 10-micron pitch Ge-on-Si SPAD pixel array achieves a photoelectric conversion efficiency of 33.8% at a wavelength of 1300 nm and 23.3% at 1550 nm in a room temperature environment.
Sony Semiconductor
This paper presents a 10μm pitch back-illuminated Ge-on-Si SPAD pixel array that achieves a photoelectric conversion efficiency of 33.8% at 1300 nm and 23.3% at 1550 nm while suppressing DC resistance in a room temperature environment. The lidar equipped with this SPAD successfully verified the ranging performance in indoor and outdoor environments up to 18 meters without differences.
42-2 A 120dB dynamic range 3D stacked dual-stage LOFIC CMOS image sensor with illuminance adaptive signal selection function
Northeastern University
This study proposes a 3D stacked dual-stage lateral overflow integration capacitor (LOFIC) CMOS image sensor with an illuminance adaptive signal selection function. To reduce the high data rate of traditional wide dynamic range sensors, this study introduces an illuminance adaptive signal selection circuit that non-destructively measures light intensity through the electrons accumulated in the first stage of LOFIC. This design allows the sensor to selectively output the optimal signal (single or dual path) among three signal paths, significantly reducing the data rate while maintaining a wide dynamic range. Additionally, a 3D stacked silicon trench capacitor structure achieves over 8.6Me- of full well capacity (FWC) at a 5.6μm pixel pitch. The measured chip achieves a dynamic range of 120 dB and a maximum SNR of 67.5 dB in selective signal readout mode.
42-3 A 129 dB dynamic range three-channel readout CMOS image sensor with full well capacity enhancement technology
Sony Semiconductor
We have launched a 2.1μm pixel CMOS image sensor for automotive applications, achieving a 129 dB single exposure dynamic range through triple readout technology. The advanced sub-pixel architecture integrates FDTI, equivalent doping, and 3D-MIM technology, significantly enhancing full well capacity. This sensor supports seamless triple image synthesis, with a signal-to-noise ratio of 29 dB at the junction, suitable for high-temperature automotive environments.
42-6 A high conversion gain low dark noise dual-layer transistor pixel stack CIS based on SOI FinFET technology
Sony Semiconductor
This study employs silicon-on-insulator (SOI) FinFET technology to develop a dual-pixel (DP) CIS with a dual-layer transistor pixel stack structure at 0.8μm. Using a body-less structure SOI FinFET on an embedded oxide layer as the pixel transistor reduces the parasitic capacitance of the floating diffusion (FD) junction, thereby enhancing conversion gain and noise characteristics. Compared to traditional pixel FinFETs, SOI FinFETs achieve superior transconductance and source follower gain. The 0.8μm DP CIS equipped with SOI FinFET validates effective solutions to the challenges associated with this structure.
42-7 A 0.43μm four-pixel CMOS image sensor based on three-wafer stacking and dual backside deep trench isolation technology
TSMC
In traditional dual-wafer stacked CMOS image sensors, reducing the pixel pitch to below 0.5μm poses significant challenges due to the limited silicon area shared by photodiodes, isolation regions, and associated functional transistors, while maintaining excellent pixel performance. This study proposes and applies several advanced pixel technologies: three-wafer stacking, dual backside deep trench isolation technology, and enhanced composite metal grid technology, successfully achieving the world’s smallest 0.43-micron pitch four photodiode pixels, achieving excellent performance metrics of 6000e- FWC, 1.3e-/s dark current, and 1.5e-rms readout noise while maintaining constant conversion gain.
42-8 A dual-layer 0.7μm pitch Dual PD pixel CMOS image sensor using super photonic color router technology
Samsung
This paper presents the world’s smallest 0.7μm pitch Dual PD (dual photodiode) pixel. We integrated dual-layer pixels solely through a hybrid copper-copper bonding process without introducing pixel-level deep contacts. By optimizing the layout of the copper pad layer, we effectively suppressed capacitive coupling between adjacent floating diffusion nodes, maintaining conversion gain comparable to that of a 0.7μm pitch single-layer single photodiode pixel. Utilizing multi-focus super photonic color router (MPCR) technology, we successfully overcame the degradation issue of autofocus (AF) separation ratio.
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Interpretation: Apple’s SPAD “SPAD Detector with Modulation Sensitivity” Patent
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