In-Depth Hardware Preparation and Planning Before starting the project, hardware selection and planning are crucial. In addition to considering the type of PCIe interface on the development board, attention must also be paid to its logic resources, storage bandwidth, etc. Taking Xilinx’s KCU105 development board as an example, it not only has a high-speed PCIe … Read more
This blog post mainly provides a simple demonstration of the steps for implementing partial reconfiguration based on PCIe (MCAP). If there are any errors, please feel free to criticize and correct them. It is worth noting that partial reconfiguration based on PCIe can only be achieved on the UltraScale and UltraScale+ series chips. The specific … Read more
Chiplet technology and NoC technology have become important methods to address the limitations of Moore’s Law. Modern CPU chips no longer use ordinary IO interfaces; instead, they utilize a standard NoC bus interface that can connect to dedicated NoC bus DIEs (tentatively referred to as IO DIEs) using Chiplet technology. By integrating multiple CPU cores … Read more
Title: Design and Implementation of PCIe RP System Based on Cortex-M3 Core XU Junjie, WEI Jinghe, LIU Guozhu, HE Jian, ZHANG Zheng (National Key Laboratory of Integrated Circuits and Microsystems) Abstract: The Peripheral Component Interconnect Express (PCIe) and Serial Rapid IO (SRIO) are mainstream high-speed communication interface protocols. In big data application scenarios represented by … Read more
Linus Torvalds: Due to family reasons, I am still traveling, so this timing for rc3 is a bit unusual, but on the East Coast, it is now (almost) afternoon, so strictly speaking, the usual Sunday afternoon schedule still applies. As expected, rc3 ended up being slightly larger than usual to balance the small rc2. Yes, … Read more
Artificial intelligence requires four networks: The computing structure connects AI accelerators, GPUs, CPUs, and other components within servers. This structure is designed for high-speed operation over short distances, typically relying on copper cables using PCIe or proprietary interfaces like NVLink. The backend network connects the aforementioned servers to AI clusters using interconnected network switches and … Read more
Fill in the DTS based on the schematic The schematic describes the hardware from the perspective of IO signals, which are strongly correlated with the PHY’s index. As mentioned earlier, the controller and PHY index of the RK3588 may not be consistent, so special attention is needed when reviewing the schematic. Here are some suggestions … Read more
Chip Resource Introduction The RK3588 has a total of 5 PCIe controllers, with the same hardware IP but different configurations. One of them is a 4-Lane DM mode that can be used as an EP, while another is a 2-Lane and 3 single-Lane controllers that can only be used as RC. The RK3588 has two … Read more
In the merge window of Linux 6.17, the PCIe subsystem has undergone a new round of updates. Although this update is not the most talked-about in recent years, it still introduces several noteworthy enhancements, including support for new platform controllers, improvements in driver quality, and optimizations in resource management. Overview of Key Updates 1. Update … Read more
In the previous article (Implementing a PCIe Device in Qemu: Implementing Function Level Reset (FLR)), we added the FLR functionality to the PCIe device simulated in Qemu and triggered the reset operation of the device by writing to the PCIe configuration space using windbg. However, the FLR triggered by manually writing to the configuration space … Read more