Chiplet technology and NoC technology have become important methods to address the limitations of Moore’s Law. Modern CPU chips no longer use ordinary IO interfaces; instead, they utilize a standard NoC bus interface that can connect to dedicated NoC bus DIEs (tentatively referred to as IO DIEs) using Chiplet technology. By integrating multiple CPU cores … Read more
In the previous article: AI System – 22 Introduction to AI Chip Storage, various storage types were discussed, but when the Core accesses data, it often encounters data consistency issues, which have already been successfully identified as common sources of errors in software, especially the inconsistencies seen between heterogeneous cores and multi-core data inconsistencies, leading … Read more
Hello everyone, welcome to my column. In previous articles, we explored the benefits of Thread-Level Parallelism (TLP) and the classifications of TLP architectures. Today, let’s learn about the cache coherence problems faced by shared memory architectures. Table of Contents 1. Shared Memory Architecture 2. Cache Coherence Problems Table of Content Mind Map 01Shared Memory ArchitectureShared … Read more