1. Mod R/M Byte Encoding Mechanism 1.1 Basic Structure The Mod R/M byte is a core component of x86 instruction encoding, dividing the 8 bits into three fields: Mod (2 bits): Specifies the addressing mode and offset type Reg/Opcode (3 bits): Specifies the register or opcode extension R/M (3 bits): Specifies the second register or … Read more
Function and Significance of Operand Size Prefix Historical Background and Design Principles The x86 processor family has evolved from 16-bit to 32-bit and then to 64-bit. To maintain backward compatibility, Intel introduced the operand size prefix mechanism: During the 8086/8086 Era: 256 opcodes were almost entirely used for 8-bit and 16-bit operands During the 80386 … Read more
The programming puzzle game TIS-100 was developed by Zachtronics and was first released in July 2015 for Windows, macOS, and Linux platforms, with an iPadOS port released in January 2016. Players can print the TIS-100 reference manual provided by the game, which details the internal workings of the TIS-100, reviving the artistic aesthetics of computer … Read more
Basics of Instruction Encoding The process of translating assembly language instructions into machine language is called instruction encoding, while the process of converting machine instructions back to assembly language is called instruction decoding. The Intel x86 architecture employs a CISC (Complex Instruction Set Computer) design, making its instruction encoding system relatively complex yet flexible. x86 … Read more
1. Original English Source CodeIt can be seen that without comments, it is difficult to understand, and over time it is easy to forget, especially since English is not the native language!2. Modifying the English of 1 to Chinese MeaningAfter understanding the basic knowledge of assembly in the same way, it can be more easily … Read more
1. Overview of Single-Byte Instructions 1.1 Basic Concepts A single-byte instruction refers to an instruction that contains only the opcode field and has no explicit operands. These instructions typically have the following characteristics: The operand is implicit in the instruction The instruction length is fixed at 1 byte High execution efficiency 1.2 Common Examples of … Read more
Overview of Exception Masking In the x86 architecture, the Floating Point Unit (FPU) provides a set of exception handling mechanisms. By default, all floating-point exceptions are masked, which means that when an exception occurs, the processor provides a default result and continues execution without interrupting the program flow. FPU Control Word Structure The FPU control … Read more
1. Fill in the blanks 1. (P64) Assembly language instructions for microcontrollers typically consist of opcodes and operands, and can also consist solely of opcodes. 2. (P68) In the base plus index addressing mode, the data pointer DPTR or program counter PC is used as the base register, and accumulator A is used as the … Read more
If you don’t want to read the rest, just send “whitespace” to the backend, and scan the mini program code. Since the inception of assembly language, many students have requested a whitespace version. Although some hidden answer solutions can be found online, they have compatibility issues with elegantbook to varying degrees. After many attempts, I … Read more
The Cortex-M3/M4 is the most mainstream ARM core in embedded development, widely used in microcontrollers such as STM32. Its assembly language follows the RISC architecture’s “reduced and efficient” design philosophy. This article explains the core logic of ARM assembly step by step, from core registers to common instructions, and practical examples. 1. Core Registers (“Operation … Read more