Review Points and Answers for Embedded System Principles and Applications
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Chapter 3
1. The ARM instruction set includes six types of instructions: branch instructions, data processing instructions, status register access instructions,
data access instructions, coprocessor instructions, and exception handling instructions.
3. The ARM instruction set and the Thumb instruction set have two common points: first, they both have a large number of registers,
which can be used for various purposes; second, access to memory can only be done through Load/Store instructions.
4. The orthogonal instruction set has the following characteristics:
(1) The vast majority of instructions in the instruction set have the same length.
(2) The length of the opcode and the addressing fields of the operands is relatively stable.
(3) In the addressing fields, all register addressing can be replaced.
5. The ARM processor has three instruction sets: the 32-bit ARM instruction set, the 16-bit Thumb instruction set, and the 8-bit Jazelle instruction set.
6. The advantages of multi-register transfer instructions: they are more efficient than single-register transfer instructions in data block operations, context switching, and stack operations, but the downside is increased interrupt latency.
7. Briefly describe the processor’s response when entering an exception and the operations that need to be performed when exiting the exception:
Processor response: (1) Save the content of CPSR to the SPSR of the exception interrupt mode to be executed (2)
Set the mode field bits in the current program status register CPSR (3) Save the address of the next instruction of the program at the time of the exception to the new exception mode’s R14 register (4) Force the program counter to be assigned a value, so that the program starts executing the interrupt service subroutine from the vector address corresponding to the exception.
Operations when exiting the exception are as follows:
(1) All modified user registers must be restored from the handler’s protected stack (2) Restore the CPSR register of the interrupted program at the moment of interruption (3) Return to the instruction location where the exception interrupt occurred or execute at the next instruction of the exception interrupt (4) Clear the interrupt disable flag in CPSR.
8. What are the characteristics of the ARM instruction set?
(1) All ARM instructions are 32 bits (2) The ARM instruction set adopts a Load-Store architecture (3)
All instructions can be conditionally executed.
9. Briefly describe the addressing modes of ARM instructions.
Register addressing, immediate addressing, register shifted addressing, register indirect addressing, base addressing, multi-register addressing, stack addressing, block copy addressing, relative addressing.