Offline Course Launch | Open Source RISC-V CPU Core Design Practice

Offline Course Launch | Open Source RISC-V CPU Core Design Practice

In 2010, the RISC-V architecture was born at the University of California, Berkeley. Thanks to its streamlined and efficient advantages, it quickly gained support from academia. After nearly a decade of development, the RISC-V architecture has received widespread recognition in both academia and industry, and is also embraced by many chip companies in China. Today, … Read more

In-Depth Analysis of the AI Industry Chain (Basic Layer)

In-Depth Analysis of the AI Industry Chain (Basic Layer)

In recent years, the artificial intelligence industry has developed rapidly. McKinsey predicts that AI could contribute 1.2 percentage points to global GDP growth over the next decade, adding $13 trillion in value to global economic activity, comparable to the introduction of transformative technologies like the steam engine during the first Industrial Revolution. From an industry … Read more

FPGA Timing Description Language

FPGA Timing Description Language

First, let’s clarify what is meant by “timing” here, which refers to the logical relationships of a set of signals, rather than timing parameters like steptime and holdtime. If you want to understand why this article exists, please refer to the series “Where is FPGA Going” and “What HLS Does FPGA Need”. Here, we focus … Read more

How to Achieve Low Power Design in Verilog?

How to Achieve Low Power Design in Verilog?

Welcome FPGA engineers to join the official WeChat technical group. Clickthe blue textto follow us at FPGA Home – the best and largest pure FPGA engineer community in China. When designing chips, the first thing to focus on is the chip’s PPA (Performance, Power, Area). This article discusses the second P, Power consumption, and how … Read more

Implementing Next-Generation In-Vehicle Infotainment Systems

Implementing Next-Generation In-Vehicle Infotainment Systems

The automotive industry is rapidly evolving, driven by new technologies, particularly the emergence of regional architectures, optimization of ADAS sensors, and the increasing use of high-quality displays in vehicles, making cars smarter than ever before. Manufacturers urgently need solutions that can help them innovate while being flexible for future updates. — TECHnalysis Research Bob O’Donnell … Read more

Accelerating Development to Mass Production of SOM Edge AI Products

Accelerating Development to Mass Production of SOM Edge AI Products

According to a report by Electronic Enthusiasts (by Cheng Wenzhi), the product development cycle is often quite short. Therefore, in China, both solution providers and terminal manufacturers prefer highly integrated chips, which speed up the development of new products.System on Module (SOM) is a highly integrated product. It is actually a miniaturized embedded board, about … Read more

A New RISC-V Architecture Leading Edge AI

A New RISC-V Architecture Leading Edge AI

👆If you wish to meet often, feel free to star 🌟 and bookmark it! Source: Contentcompiled by Semiconductor Industry Observation (ID: icbank) from allaboutcircuits, thank you. Red Semiconductor announced the launch of a multifunctional intrinsic structured computing (VISC) architecture for RISC-V. VISC is an extension of RISC-V IP that accelerates complex algorithms and adds parallel … Read more

Understanding JTAG Protection with TVS in Xilinx FPGA

Understanding JTAG Protection with TVS in Xilinx FPGA

Exploring the JTAG interface of the 7-series Xilinx FPGA and Zener diode protection When I was selecting the 7-series Xilinx FPGA for a new PCB design, I was unsure about the design of the JTAG interface. To find a reliable reference, I reviewed several schematic diagrams of Xilinx evaluation boards, among which the schematic of … Read more

RISC-V Processor and FPGA Reusing JTAG

RISC-V Processor and FPGA Reusing JTAG

Click to follow for more exciting content!! 01PARTIntroduction This article provides a brief explanation of the usage of BSCAN based on the Spartan-6 and Kintex-7 series of FPGAs, using the K735 development board and LS-Extended development board; the software used includes riscv-openocd and riscv-gdb (included in the toolchain). Principle Explanation02PART BSCAN stands for JTAG-boundary-scan, which … Read more

Detailed Explanation of Zynq JTAG Mode Configuration and Boot Process

Detailed Explanation of Zynq JTAG Mode Configuration and Boot Process

Follow and star our official account for exciting content Source: https://blog.csdn.net/weixin_39847099/article/details/111802365Organized by: ZYNQ | Xiao Mo The JTAG Configuration Process of Zynq When first learning Zynq, I believe everyone, like me, follows the usual practice of opening the Vivado software, setting up the programmable logic (PL) part of Zynq, exporting the hardware deployment, then opening … Read more