FPGA Clock Analysis The clock system is the “heart” of FPGA design, and its performance directly determines the system’s timing margin, operating frequency, and stability. Effective clock analysis can help engineers identify timing bottlenecks, optimize clock architecture, and ensure reliable operation of the design at the target frequency. This article will systematically analyze the composition, … Read more
Wang Zhen – China Information Communication Technology： In this week’s collaborative learning, I systematically studied Chapter 7 of the book Analog-to-Digital Conversion, which mainly includes topics on time-domain and frequency-domain sampling, modulation and chopping, recovery of sampled data, noise, jitter, etc., further understanding the sampling circuits in ADC. Bu Zeng – Huawai: This week, I … Read more
Situation 1: Slave Loses Synchronization Causes: 1. The EtherCAT task may be experiencing excessive jitter; 2. There may be issues with the network cable, such as using unshielded cables or poor connections; individual slaves may also have problems. Exclusion of Possible Causes: ① Check the logs; if the following log entries are present, it indicates … Read more
According to industry experts such as PROCENTEC, applications based on RS-485 fieldbus technology (PROFIBUS®) are continuously growing, and industrial Ethernet (PROFINET) applications are also rapidly increasing. In 2018, a total of 61 million PROFIBUS fieldbus nodes were installed globally, with a 7% year-on-year growth in PROFIBUS process automation (PA) devices. The installation base for PROFINET … Read more
Let’s illustrate this issue with a specific example. How does a typical task system handle information in embedded systems? The process looks like this: • Retrieve new data • Filter/process data • Output data Pretty straightforward, right? We know that for real-time embedded system design, the main goal is determinism and minimizing jitter. The three … Read more
Application of Real-Time Oscilloscopes in New Generation Optical Interface Time Domain Testing Introduction: When it comes to time domain testing of optical interface metrics, engineers often mention the sampling oscilloscope. This is because sampling oscilloscopes have unparalleled advantages in signal integrity: high bandwidth, low noise, and minimal quantization error (high vertical resolution). However, the downside … Read more
Let’s illustrate this issue with a concrete example. How does a typical task system handle information in embedded systems? The process looks like this: • Retrieve new data • Filter/Process data • Output data Pretty straightforward, right? We know that for real-time embedded system design, the main goal is determinism and minimizing jitter. The three … Read more
An eye diagram, as the name suggests, is a graphical representation that resembles an eye. How is it formed? This brings us to the persistence mode of an oscilloscope. The refresh rate of our naked eyes is only 60Hz, which sometimes makes it difficult to detect occasional abnormal signals. The persistence mode can superimpose and … Read more
Jitter is the short-term variation of a digital signal’s timing relative to its nominal value. There are two main types of jitter: random jitter and deterministic jitter. Random jitter is unbounded, meaning its value continues to increase as the measurement duration increases, and it is related to random processes such as noise. Deterministic jitter, on … Read more
Author Introduction Dr. Liu, Ph.D. from University of Electronic Science and Technology, an expert in microarchitecture. 1. Background The clock circuit is the most basic circuit in the chip. The performance of the clock circuit is related to whether all the modules in the SoC can achieve the expected goals, such as the main frequency … Read more