PCB Layout Design Review Elements
01DFM Requirements for Layout
1 The preferred process route has been determined, and all components have been placed on the board.
2 The coordinate origin is at the intersection of the left and bottom extension lines of the board frame, or the lower left pad of the leftmost socket.
3 The actual size of the PCB and the positions of the components match the process structure element diagram, and the layout of components in areas with height restrictions meets the requirements of the structural element diagram.
4 The positions of DIP switches, reset devices, indicator lights, etc., are appropriate, and the pull handle bar does not interfere with surrounding components.
The outer frame of the board has a smooth arc of 197 mil, or is designed according to the structural dimension diagram.
6 The standard board has a 200 mil process edge; the left and right sides of the backplane have a process edge greater than 400 mil, and the top and bottom sides have a process edge greater than 680 mil. The placement of components does not conflict with the window positions.
7 All additional holes that need to be added (ICT positioning holes of 125 mil, pull handle holes, oval holes, and fiber optic support holes) are not omitted and are set correctly.
8 The pin spacing, component orientation, component spacing, and component library of components processed through wave soldering consider the requirements of wave soldering processing.
9 The spacing of component layouts meets assembly requirements: surface mount devices greater than 20 mil, ICs greater than 80 mil, BGAs greater than 200 mil.
10 The distance from the component surface to the press-fit component is greater than 120 mil, and there are no components in the soldering area of the press-fit component.
11 There are no short components between tall components, and no surface mount components or short, small through-hole components are placed within 5 mm of components taller than 10 mm.
12 Polarized components have polarity silk screen markings. Components of the same type with polarity are oriented in the same direction along the X and Y axes.
13 All components have clear markings, with no ambiguous markings such as P* or REF.
14 The surface with surface mount components has three positioning marks arranged in an “L” shape. The center of the positioning mark is more than 240 mil from the edge of the board.
15 If panelization is required, the layout considers ease of panelization and PCB processing and assembly.
16 Boards with notches (irregular edges) should be filled using milling grooves and stamp holes. Stamp holes are non-metalized voids, generally with a diameter of 40 mil and an edge distance of 16 mil.
17 Test points for debugging have been added in the schematic and are appropriately placed in the layout.
Thermal Design Requirements for Layout
18 Heating components and exposed components should not be placed close to wires and thermal-sensitive components; other components should also be kept at a suitable distance.
19 The placement of heat sinks considers convection issues, with no tall components interfering within the projection area of the heat sink, and the range is marked on the mounting surface with silk screen.
20 The layout considers reasonable and smooth heat dissipation channels.
21 Electrolytic capacitors should be placed at a suitable distance from high-heat components.
22 Consideration is given to the heat dissipation issues of high-power components and components under the board.
02Signal Integrity Requirements for Layout
23 Start matching should be close to the transmitting device, and end matching should be close to the receiving device.
24 Decoupling capacitors should be placed close to relevant components.
25 Crystals, oscillators, and clock driver chips should be placed close to relevant components.
26 High-speed and low-speed, digital and analog should be laid out separately by module.
27 The topology of the bus should be determined based on analysis simulation results or existing experience to ensure it meets system requirements.
28 If it is a redesign, simulation should be conducted based on signal integrity issues reflected in the test report, and solutions should be provided.
29 The layout of synchronous clock bus systems should meet timing requirements.
03EMC Requirements
30 Inductive components such as inductors, relays, and transformers that are prone to magnetic field coupling should not be placed close to each other. When there are multiple inductive coils, their directions should be perpendicular to avoid coupling.
31 To avoid electromagnetic interference between sensitive components on the soldering surface of the single board and adjacent single boards, sensitive components and strong radiation components should not be placed on the soldering surface.
32 Interface components should be placed close to the edge of the board, and appropriate EMC protection measures (such as shielded enclosures, power ground voids, etc.) should be taken to enhance the EMC capability of the design.
33 Protection circuits should be placed near interface circuits, following the principle of protection before filtering. Masembly’s surface mount knowledge classroom introduces professional surface mount knowledge in simple terms. Masembly Technology is the first nationwide provider of one-stop services for PCB (Masembly Knowledge Classroom) sample board production, component procurement, and surface mount!
34 Components with high transmission power or particularly sensitive components (such as oscillators, crystals, etc.) should be placed more than 500 mil away from shielding bodies and shielded enclosures.
35 A 0.1uF capacitor is placed near the reset line of the reset switch, and the reset device and reset signal are kept away from other strong components and signals.
Layer Setup and Power Ground Segregation Requirements
37 When two signal layers are directly adjacent, vertical wiring rules must be defined.
38 The main power layer should be as close as possible to its corresponding layer, and the power layer should meet the 20H rule.
39 Each wiring layer should have a complete reference plane.
40 Multi-layer boards should be stacked symmetrically with core materials to prevent uneven copper foil density distribution and asymmetric dielectric thickness from causing warping.
41 The board thickness should not exceed 4.5mm. For boards thicker than 2.5mm (backplanes greater than 3mm), confirmation from process personnel is required to ensure that PCB processing, assembly, and equipment are not problematic. The thickness of PC cards is 1.6mm.
42 When the thickness-to-diameter ratio of vias is greater than 10:1, confirmation from the PCB manufacturer is required.
43 The power and ground of optical modules should be separated from other power and ground to reduce interference.
44 The power and ground handling of critical components should meet requirements.
45 When impedance control is required, the layer setup parameters should meet the requirements.
Power Module Requirements
46 The layout of the power section ensures smooth and non-crossing input and output lines.
47 When the single board supplies power to the backplane, the corresponding filtering circuit should be placed near the power outlet of the single board and the power inlet of the backplane.
04Other Requirements
48 The layout considers the smoothness of overall routing, and the main data flow direction is reasonable.
49 Adjust the pin assignments of resistors, FPGAs, EPLDs, bus drivers, etc., based on the layout results to optimize routing.
50 The layout considers appropriately increasing the space in densely routed areas to avoid routing issues.
51 If special materials, special components (such as 0.5mm BGA, etc.), or special processes are used, the delivery time and manufacturability have been fully considered, and confirmation from the PCB manufacturer and process personnel has been obtained.
52 The pin correspondence of the backplane connector has been confirmed to prevent misalignment of the backplane connector direction and orientation.
53 If there are ICT testing requirements, the feasibility of adding ICT test points should be considered during layout to avoid difficulties in adding test points during the routing phase.
54 When high-speed optical modules are included, the layout should prioritize the optical port transceiver circuit.
55 After the layout is completed, a 1:1 assembly diagram has been provided for the project personnel to verify the correctness of component packaging selection against the physical components.
56 The window areas have been considered for inner layer planes to be recessed, and appropriate no-routing zones have been set.
05Three Special Routing Techniques in PCB Layout
Today, I will discuss PCB layout routing techniques from three aspects: right-angle routing, differential routing, and serpentine routing:
1. Right-Angle Routing (Three Aspects)
The impact of right-angle routing on signals is mainly reflected in three aspects: first, corners can be equivalent to capacitive loads on transmission lines, slowing down the rise time; second, impedance discontinuities can cause signal reflections; third, the EMI generated by right-angle tips can become a focal point for high-speed issues in RF design fields above 10GHz.
2. Differential Routing (“Equal Length, Equal Spacing, Reference Plane”)
What is a differential signal? Simply put, it is when the driver sends two equal and opposite signals, and the receiver determines the logic state “0” or “1” by comparing the difference between these two voltages. The pair of traces carrying the differential signal is called differential routing. The most obvious advantages of differential signals compared to ordinary single-ended signals are reflected in the following three aspects:
1. Strong anti-interference capability, as the coupling between the two differential traces is good; when external noise interference exists, it is almost simultaneously coupled to both traces, and the receiver only cares about the difference between the two signals, so the common-mode noise from the outside can be completely canceled out.
2. Effective suppression of EMI; similarly, due to the opposite polarity of the two signals, their radiated electromagnetic fields can cancel each other out, and the tighter the coupling, the less electromagnetic energy is released to the outside.
3. Accurate timing positioning; since the switching changes of differential signals occur at the intersection of the two signals, unlike ordinary single-ended signals that rely on high and low threshold voltages for judgment, they are less affected by process and temperature, reducing timing errors, and are also more suitable for low-amplitude signal circuits. The currently popular LVDS (low voltage differential signaling) refers to this small amplitude differential signal technology.
3. Serpentine Routing (Adjusting Delay)
Serpentine routing is a commonly used routing method in layout. Its main purpose is to adjust the delay to meet the system timing design requirements. The two key parameters are parallel coupling length (Lp) and coupling distance (S). Clearly, when signals are transmitted on serpentine traces, coupling occurs between the parallel segments, in differential mode; the smaller S is and the larger Lp is, the greater the coupling degree, which may lead to reduced transmission delay and significantly lower signal quality due to crosstalk. The mechanism can be referenced in the analysis of common-mode and differential-mode crosstalk. Here are some suggestions for layout engineers when dealing with serpentine routing:
1. Try to increase the distance between parallel segments (S), at least greater than 3H, where H refers to the distance from the signal trace to the reference plane. In simple terms, this means routing around large bends; as long as S is large enough, the coupling effect can be almost completely avoided.
2. Reduce the coupling length Lp; when twice the Lp delay approaches or exceeds the signal rise time, the crosstalk generated will reach saturation.
3. The delay caused by serpentine routing in strip-line or embedded micro-strip is less than that in micro-strip routing. Theoretically, strip-line will not be affected by differential-mode crosstalk on the transmission rate.
4. For high-speed signals and those with strict timing requirements, serpentine routing should be avoided, especially not in small areas.
5. Arbitrary angle serpentine routing can often be used to effectively reduce mutual coupling.
6. In high-speed PCB design, serpentine routing does not have any filtering or anti-interference capability; it can only reduce signal quality, so it should only be used for timing matching and no other purpose.
7. Sometimes, consider using spiral routing; simulations show that its effect is better than normal serpentine routing.
06Electromagnetic Compatibility in PCB Technology
Electromagnetic compatibility (EMC) refers to the ability of electronic devices to operate effectively in various electromagnetic environments. The purpose of EMC design is to ensure that electronic devices can suppress various external interferences, operate normally in specific electromagnetic environments, and reduce the electromagnetic interference that electronic devices themselves generate on other electronic devices. Electromagnetic compatibility in printed circuit board (PCB) design involves multiple factors, which will be elaborated on mainly from three parts, with specific selections considering various factors.
1. Overall Layout and Component Arrangement of the Printed Circuit Board
1. The success of a product depends on both internal quality and overall aesthetics; both must be relatively perfect for the product to be considered successful. On a PCB, the layout of components should be balanced, orderly, and not top-heavy or bottom-heavy, with as few vias as possible; the optimal shape for a circuit board is rectangular, with an aspect ratio of 3:2 or 4:3; 4-layer boards have 20dB lower noise than double-sided boards, and 6-layer boards have 10dB lower noise than 4-layer boards. When economic conditions allow, multi-layer boards should be used as much as possible.
2. The circuit board is generally divided into analog circuit areas (sensitive to interference), digital circuit areas (sensitive to interference and also generate interference), and power drive areas (interference sources), so the board should be reasonably divided into three areas.
3. Components should generally be selected for low power consumption and good stability, and high-speed components should be used sparingly.
4. There are rules for traces: if conditions allow, use wide traces instead of narrow ones; high-voltage and high-frequency traces should be rounded and should not have sharp corners; turns should not be made at right angles. Ground lines should be as wide as possible, preferably using large areas of copper pour, which significantly improves grounding issues.
5. External clocks are high-frequency noise sources that can interfere with the application system and may also generate interference to the outside, causing electromagnetic compatibility testing to fail. In applications with high reliability requirements, selecting low-frequency microcontrollers is one of the principles for reducing system noise. For example, the 8051 microcontroller has a minimum instruction cycle of 1μs, with an external clock of 12MHz, while a similarly fast Motorola microcontroller system clock only requires 4MHz, making it more suitable for industrial control systems. In recent years, some manufacturers producing 8051-compatible microcontrollers have adopted new technologies to reduce the external clock requirement to one-third of the original without sacrificing computational speed. Similarly, Motorola microcontrollers in the newly launched 68HC08 series and their 16/32-bit microcontrollers generally use internal phase-locked loop technology to reduce the external clock frequency to 32KHz while increasing the internal bus speed to 8MHz or higher.
6. Routing should have a reasonable direction: for example, input/output, AC/DC, strong/weak signals, high-frequency/low-frequency, high-voltage/low-voltage, etc. Their directions should be linear (or separated) and should not intermingle to prevent mutual interference. The best direction is straight, but this is generally difficult to achieve; the worst direction is circular. For DC, small signal, and low voltage PCB design, the requirements can be lower. Therefore, “reasonable” is relative. The routing direction between layers should generally be perpendicular. The entire board should not be overly uniform; components should not be crowded together unnecessarily.
7. In terms of component arrangement, as with other logic circuits, related components should be placed as close together as possible to achieve better noise immunity. Clock generators, crystals, and the clock input of the CPU are prone to noise and should be placed close together, especially avoiding routing signal lines under the crystal. Components that easily generate noise, small current circuits, and large current circuits should be kept as far away from logic circuits as possible; if feasible, they should be placed on separate circuit boards. This is very important.
2. Grounding Techniques
1. There are many similarities and differences in the design and wiring methods of analog and digital circuits. In analog circuits, due to the presence of amplifiers, even the smallest noise voltage generated by wiring can cause severe distortion of the output signal. In digital circuits, the noise tolerance for TTL is 0.4V to 0.6V, and for CMOS, it is 0.3 to 0.45 times Vcc, so digital circuits have stronger anti-interference capabilities. A good choice of power and ground bus methods is an important guarantee for the reliable operation of instruments, as many interference sources are generated through power and ground buses, with ground noise interference being the largest.
2. Digital ground and analog ground should be separated (or grounded at one point), and ground lines should be widened according to current; generally, the thicker, the better (a 100 mil line can carry about 1 to 2A of current). The reasonable choice of line widths is ground line > power line > signal line.
3. Power lines and ground lines should be as close as possible, and the power and ground on the entire printed board should be distributed in a “zigzag” pattern to ensure balanced distribution of line currents.
4. To reduce inter-line crosstalk, the distance between printed lines can be increased if necessary, inserting some zero-volt lines as isolation between lines, especially between input and output signals.
3. Decoupling, Filtering, and Isolation Techniques
1. Decoupling, filtering, and isolation are three commonly used measures for hardware anti-interference.
2. A 10~100uF electrolytic capacitor should be connected across the power input. If possible, a capacitor greater than 100uF is better; in principle, each integrated circuit chip should have a 0.01pF ceramic capacitor arranged; if the printed board space is insufficient, one 1~10pF capacitor can be arranged for every 4~8 chips; for devices with weak anti-noise capability and large power changes when turned off, such as RAM and ROM storage devices, decoupling capacitors should be directly connected between the chip’s power and ground lines;
3. Filtering refers to classifying various signals according to frequency characteristics and controlling their direction. Commonly used types include various low-pass filters, high-pass filters, and band-pass filters. Low-pass filters are used on incoming AC power lines to allow 50Hz AC to pass smoothly while directing other high-frequency noise to ground. The configuration index for low-pass filters is insertion loss; if the selected low-pass filter has too low insertion loss, it will not suppress noise effectively, while too high insertion loss will lead to “leakage” and affect the safety of the system. High-pass and band-pass filters should be selected based on the signal processing requirements in the system.
4. A typical signal isolation method is optical isolation. Using optical isolators to isolate the input and output of the microcontroller prevents interference signals from entering the microcontroller system, while also preventing the noise from the microcontroller system from propagating out. Shielding is used to isolate spatial radiation; for components with particularly high noise, such as switch-mode power supplies, using metal enclosures can reduce the interference of noise sources on the microcontroller system. For particularly noise-sensitive analog circuits, such as high-sensitivity weak signal amplification circuits, shielding can be applied. Importantly, the metal shield itself must be connected to a true ground.
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