1. Introduction to FFT Algorithm and Vivado FFT IP Core

1. What is FFT?

FFT (Fast Fourier Transform) is an efficient algorithm for computing the Discrete Fourier Transform (DFT).

The mathematical definition of DFT is:

Direct computation of DFT requires N multiplications and additions, while FFT reduces the complexity to:, significantly improving computational efficiency, making it the most commonly used spectral analysis algorithm in Digital Signal Processing (DSP).

2. Core Idea of FFT

FFT uses the “divide and conquer” approach to decompose an N-point DFT into multiple smaller DFTs. For example, using Radix-2:

Split the input sequence into “even” and “odd” terms;
Perform N/2-point FFT on both parts;
Finally, combine the results using the “Twiddle Factor”.

The formula is:

Where:

is the FFT of the even sequence;
is the FFT of the odd sequence;
is the Twiddle Factor.

3. Common Types of FFT

Type	Description
Radix-2	The classic binary FFT, where the number of points N must be a power of 2.
Radix-4 / Mixed-Radix	Higher-order decomposition, suitable for higher performance scenarios.
Real FFT	An optimized version for real input signals (reducing computational load).
Inverse FFT (IFFT)	The inverse transform of FFT, used to recover time-domain signals from the frequency domain.

4. Introduction to Vivado FFT IP Core

The FFT IP provided by Vivado is named “Fast Fourier Transform”, supporting:

FFT / IFFT operations;
Real or complex input;
Configurable number of points, data width, and scaling mode;
Multiple interfaces (including AXI4-Stream).

This IP is optimized by Xilinx to fully utilize the DSP Slice and Block RAM of the FPGA, achieving high-performance streaming FFT operations.

2. Interpretation of FFT IP Core Configuration Page

Configuration

FPGA Notes 3: Introduction to FFT Algorithm and Vivado FFT IP Core — Configuration

Number of Channels

Specify the number of parallel FFT channels to be processed simultaneously (1 to 12, generally select 1, selecting more than 1 will automatically reuse hardware internally).

Multi-channel operation is usually used to save logic resources (shared control logic), but may reduce the maximum clock frequency.
Note: If you plan to use floating-point format later, the number of channels must be set to 1.

Transform Length

Meaning: Number of points in FFT
Supports powers of 2 between 8 and 65536.
A larger transform length will bringhigher frequency resolution, higher latency (because the data must be fully input before the first result is output), andhigher resource usage.

Architecture Configuration

The values in this section are mainly used for auxiliary tools to calculate latency and automatically select architecture,they do not directly constrain the clock.

Target Clock Frequency (MHz): The target clock frequency. Fill in the FPGA clock frequency. This value is used for microsecond calculations in the latency tab, for Vivado to select the appropriate implementation architecture, and to evaluate resource consumption and performance.
Target Data Throughput (MSPS): The target data throughput. Tells the IP how many MSPS (Million Samples Per Second) need to be processed per second. If the