FPGA-Based 16×16 Dot Matrix Display Design VHDL Code Simulation

Name: FPGA-Based 16×16 Dot Matrix Display Design VHDL Code Simulation

Software: Quartus

Language: VHDL

Code Function: 16×16 Dot Matrix Display “VHDL”

1. Project Files

2. Program Files

3. Program Compilation

4. Testbench

5. Simulation Diagram

Partial code display:

LIBRARY ieee;
   USE ieee.std_logic_1164.all;
   USE ieee.std_logic_unsigned.all;
ENTITY led_16X16 IS
   PORT (
      clk   : IN STD_LOGIC;
      hang  : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);--Dot Matrix Row
      lie   : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)--Dot Matrix Column
   );
END led_16X16;
ARCHITECTURE trans OF led_16X16 IS
   TYPE type_xhdl0 IS ARRAY (0 TO 63) OF STD_LOGIC_VECTOR(15 DOWNTO 0);--Define an array with a width of 16 and a length of 64

--Encoding for "V"
   SIGNAL word_V_1  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000000000000000";
   SIGNAL word_V_2  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0111000000001111";
   SIGNAL word_V_3  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011100000001110";
   SIGNAL word_V_4  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011100000001110";
   SIGNAL word_V_5  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011100000011100";
   SIGNAL word_V_6  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0001110000011100";
   SIGNAL word_V_7  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0001110000011100";
   SIGNAL word_V_8  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0001110000111000";
   SIGNAL word_V_9  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000111000111000";
   SIGNAL word_V_10 : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000111000111000";
   SIGNAL word_V_11 : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000111001110000";
   SIGNAL word_V_12 : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000011101110000";
   SIGNAL word_V_13 : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000011101110000";
   SIGNAL word_V_14 : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000011111100000";
   SIGNAL word_V_15 : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000001111100000";
   SIGNAL word_V_16 : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000001111100000";
--Encoding for "H"    
   SIGNAL word_H_1    : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0110000000000110";
   SIGNAL word_H_2    : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0110000000000110";
   SIGNAL word_H_3    : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0110000000000110";
   SIGNAL word_H_4    : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0110000000000110";
   SIGNAL word_H_5    : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0110000000000110";
   SIGNAL word_H_6    : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0110000000000110";
   SIGNAL word_H_7    : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0110000000000110";
   SIGNAL word_H_8    : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0111111111111110";
   SIGNAL word_H_9    : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0111111111111110";
   SIGNAL word_H_10   : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0110000000000110";
   SIGNAL word_H_11   : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0110000000000110";
   SIGNAL word_H_12   : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0110000000000110";
   SIGNAL word_H_13   : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0110000000000110";
   SIGNAL word_H_14   : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0110000000000110";
   SIGNAL word_H_15   : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0110000000000110";
   SIGNAL word_H_16   : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0110000000000110";
--Encoding for "D"    
   SIGNAL word_D_1  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011111111110000";
   SIGNAL word_D_2  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011111111111000";
   SIGNAL word_D_3  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000111100";
   SIGNAL word_D_4  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000011100";
   SIGNAL word_D_5  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000001100";
   SIGNAL word_D_6  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000001100";
   SIGNAL word_D_7  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000001100";
   SIGNAL word_D_8  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000000100";
   SIGNAL word_D_9  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000000100";
   SIGNAL word_D_10 : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000000100";
   SIGNAL word_D_11 : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000001100";
   SIGNAL word_D_12 : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000001100";
   SIGNAL word_D_13 : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000001100";
   SIGNAL word_D_14 : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000011100";
   SIGNAL word_D_15 : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000111100";
   SIGNAL word_D_16 : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011111111111000";
--Encoding for "L"    
   SIGNAL word_L_1   : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000000000";
   SIGNAL word_L_2   : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000001000";
   SIGNAL word_L_3   : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000000000";
   SIGNAL word_L_4   : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000000000";
   SIGNAL word_L_5   : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000000000";
   SIGNAL word_L_6   : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000000000";
   SIGNAL word_L_7   : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000000000";
   SIGNAL word_L_8   : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000000000";
   SIGNAL word_L_9   : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000000000";
   SIGNAL word_L_10  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000000000";
   SIGNAL word_L_11  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000000000";
   SIGNAL word_L_12  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000000000";
   SIGNAL word_L_13  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000000000";
   SIGNAL word_L_14  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011000000000000";
   SIGNAL word_L_15  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011111111111100";
   SIGNAL word_L_16  : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0011111111111100";
   
   SIGNAL word    : type_xhdl0;--Define word array to store character encoding
   
   SIGNAL clk_1   : STD_LOGIC := '0';
   SIGNAL x       : INTEGER := 0;
   
   SIGNAL hang_cnt : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
   
   SIGNAL n       : INTEGER := 0;
BEGIN