FPGA-Based AD7705 Driver Design Verilog Code Simulation

Name: FPGA-Based AD7705 Driver Design Verilog Code Simulation

Software: Quartus

Language: Verilog

Code Function: AD7705 Driver Design

1. Project Files

2. Program Files

3. Program Compilation

4. Simulation Diagram

Testbench

Simulation Diagram

Overall Simulation

Reset, continuously write 32 high levels

Sequentially write 8’h20, 8’h03, 8’h10, 8’h40

Write 8’h38, and read data

Partial code display:

module AD7705_driver(
input clk_50M,
input reset_n,//System reset signal, active low
output [15:0] AD_data_out,//Output AD data
//AD7705
input AD_DRDY_n,
input AD_dout,
output AD_CS,
output AD_clk,
output AD_din
);
assign AD_CS=0;//CS remains low
parameter s_reset=3'd0;//FFFF
parameter s_communicate_clkreg=3'd1;//8'h20
parameter s_clk_reg=3'd2;//8'h03
parameter s_communicate_setreg=3'd3;//8'h10
parameter s_set_reg=3'd4;//8'h40
parameter s_communicate_datareg=3'd5;//8'h38, read channel 1
parameter s_read_data=3'd6;//Read 16bit data
parameter s_wait_DRDY=3'd7;//Wait for DRDY==0
//Define registers
reg [7:0] communicate_clkreg=8'h20;
reg [7:0] clk_reg=8'h03;
reg [7:0] communicate_setreg=8'h10;
reg [7:0] set_reg=8'h40;
reg [7:0] communicate_datareg=8'h38;
reg [2:0] state=3'd0;
//AD_clk maximum 5M, read/write on rising edge
reg [7:0] cycle_cnt=8'd0;
reg AD_clk_reg=0;//Using 5M clock, 50/5=10;
reg [7:0] AD_clk_reg_cnt=8'd0;
always@(posedge clk_50M)
if(~reset_n) 
AD_clk_reg_cnt<=8'd0;
else
if(AD_clk_reg_cnt==8'd9)
AD_clk_reg_cnt<=8'd0;
else
AD_clk_reg_cnt<=AD_clk_reg_cnt+8'd1;
//50M divided to 5MHz
always@(posedge clk_50M)
if(AD_clk_reg_cnt>=8'd5)
AD_clk_reg<=1;
else
AD_clk_reg<=0;
reg clk_en=0;//SPI work enable
assign AD_clk=AD_clk_reg & clk_en;//5M
reg AD_din_reg=0;
assign AD_din=AD_din_reg & clk_en;
reg AD_clk_reg_buf=0;
always@(posedge clk_50M)
AD_clk_reg_buf<=AD_clk_reg;
wire AD_clk_reg_down;//Falling edge of AD_clk_reg
wire AD_clk_reg_rise;//Rising edge of AD_clk_reg
assign AD_clk_reg_down=~AD_clk_reg & AD_clk_reg_buf;//Falling edge of AD_clk_reg
assign AD_clk_reg_rise=AD_clk_reg & ~AD_clk_reg_buf;//Rising edge of AD_clk_reg
//Initialization and reading AD value state machine
reg [15:0] AD_data=16'd0;
always@(posedge clk_50M)
if(~reset_n)begin
state<=s_reset;
cycle_cnt<=8'd0;
clk_en<=0;
communicate_clkreg<=8'h20;
clk_reg<=8'h03;
communicate_setreg<=8'h10;
set_reg<=8'h40;
communicate_datareg<=8'h38;
end
else
case(state)
s_reset:begin//Reset, continuously write 32 high levels
if(AD_clk_reg_down==1)
if(cycle_cnt>8'd31)begin
cycle_cnt<=8'd0;
state<=s_communicate_clkreg;
clk_en<=0;
end
else begin
cycle_cnt<=cycle_cnt+8'd1;
AD_din_reg<=1;
state<=s_reset;