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⚡️Algorithm Simulation Effect Preview

The hardware in-chip test results using Vivado 2022.2 are as follows (217 convolution encoding and decoding Verilog development, without using IP cores):

🚀System Overview

1. 217 Convolution Encoding / Viterbi Decoding

The 217 convolution code is defined by the generating polynomial, with common generating polynomials being G1 = 111 and G2 = 101, where the numbers represent the coefficients of the polynomial in binary form.

The convolution encoder: The encoding process is completed by the convolution encoder, which consists of multiple shift registers and programmable adders. Input data is sequentially passed through the shift registers, and according to the rules of the generating polynomial, modulo 2 addition is performed with the delayed data to generate the encoded output.

Encoding rate: The 217 convolution code typically operates at a “2/7” encoding rate, meaning that every 2 input bits produce 7 encoded bits, increasing the redundancy of the data, allowing the receiver to detect and correct errors that occur during transmission.

Viterbi decoding is a maximum likelihood decoding algorithm for convolution codes. It estimates the phase offset of the signal based on the received signal and the known convolution code generating polynomial, selecting the most likely transmitted sequence as the decoding result by calculating path metrics (such as Hamming distance), thus correcting errors caused by noise during transmission and recovering the original input data.

2. 16QAM Mapping / Inverse Mapping

16QAM is formed by superimposing two independent orthogonal 4ASK signals, where 4ASK is a signal obtained by modulating a carrier with multi-level signals. It is an extension of 2ASK modulation, and compared to 2ASK, this modulation has the advantage of a higher information transmission rate. Orthogonal Amplitude Modulation combines multi-level amplitude shift keying (MASK) with orthogonal carrier modulation. 16-QAM is a signal that combines amplitude and phase shift keying.

3. Upconversion / Downconversion

The process of shifting the frequency spectrum of the baseband signal to the desired higher carrier frequency. The principle is to send the signal to be converted and a fixed frequency local oscillator signal into a nonlinear device (mixer), obtaining two frequencies that are the sum and difference of the frequencies, and then filtering to extract the upper sideband signal, completing the upconversion and modulating the baseband signal onto a high-frequency carrier for transmission.

Downconversion is the reverse process of upconversion, which shifts the frequency spectrum of the received high-frequency signal down to a lower frequency, usually intermediate frequency or baseband frequency. Similarly, it mixes with a sine wave signal generated by the local oscillator, then extracts the lower sideband signal (or further processes to obtain the baseband signal) for subsequent demodulation and other processing.

4. Frequency Offset Locking Based on PN Pilot and CORDIC

When the sender transmits data frames, it appends a known pseudo-random (PN) pilot sequence, and the receiver uses the PN pilot sequence to estimate the frequency offset of the signal. The receiver performs delay and conjugate multiplication on the received pilot data, and then uses the CORDIC algorithm for iterative rotation based on its real and imaginary parts to estimate the phase offset of the signal, thus obtaining the frequency offset value. Finally, by multiplying the received signal with a negative complex exponential function, frequency offset compensation is achieved, locking the frequency offset to zero.

5. Timing Point Extraction Based on Correlation Peaks

In the received signal, the timing point is determined by finding the correlation peak with a locally known sequence (such as a training sequence or pilot sequence). Specifically, the received signal is correlated with the local sequence, and when their phases and times align, the correlation value reaches a peak, which corresponds to the best timing point for determining the sampling moment of the signal, ensuring the accuracy of subsequent signal processing.

6. Frame Synchronization

In digital communication, information is usually organized and transmitted in frames. The purpose of frame synchronization is to determine the starting position of each frame so that the receiver can correctly demodulate the data within each frame. The structure of the transmitted frame is: frame synchronization code + information code sequence. The frame synchronization code is a code sequence with a specific pattern used by the receiver to identify the start of the frame. The frame synchronization process involves searching for the position in the received sequence that matches the frame synchronization code; once a match is found, the starting position of the frame is determined, and subsequent code elements can be correctly divided and processed according to the frame structure.

7. Sampling Decision

After determining the timing point, the received signal is sampled, and the sampled values are compared with preset decision thresholds. Based on the comparison results, the level value of the received signal is determined, thus recovering the original binary bit stream. For example, in QPSK signals, the decision is made based on the position of the sampling point in the complex plane relative to the corresponding relationships of each phase state, determining which two bits were transmitted.

✨Some Core Code

Program structure:

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