FPGA-Based Washing Machine Controller Design Verilog Code for Quartus and Zedboard

Name: FPGA-Based Washing Machine Controller Design Verilog Code for Quartus and Zedboard

Software: Quartus

Language: Verilog

Code Function:

The main tasks and basic requirements are as follows:

1. Main Tasks

Design and implement an FPGA-based washing machine controller using Verilog or VHDL for hardware description.

The controller should enable intelligent control of the washing machine’s operation process, including washing, rinsing, and spinning phases, while being able to monitor the washing machine’s status in real-time.

The controller should have human-machine interaction capabilities, allowing control via buttons or a touchscreen.

Complete the hardware design and simulation testing of the controller, followed by practical application testing.

Submit a complete project report, including design documentation, test reports, and practical application reports.

2. Basic Requirements

1. Cycle output forward, reverse, and pause signals.

2. Ability to preset washing time.

3. Ability to display the input timing.

4. Good operability and reliability.

5. Implement timed start → forward for 25s → pause for 5s → reverse for 25s → pause for 5s → if time is not up, return to “forward for 25s → pause for 5s → …”, stop when the timer expires.

This code has been verified on the Zedboard; other development boards can modify pin assignments accordingly:

1. Project Files

2. Program Files

3. Program Compilation

4. RTL Diagram

5. Pin Assignment

6. Testbench

7. Simulation Diagram

Overall simulation diagram

1K Frequency Division Module

1Hz Frequency Division Module

Control Module

Display Module

Partial Code Display:

// Control Module
module control(
input clk_1Hz,// 1Hz
input key_add,// Add button
input key_sub,// Subtract button
input key_start,// Start/Pause button
input key_reset,// Reset button
output end_led,// End indicator light
output reg D1,// Forward
output reg D2,// Reverse
output reg D3,// Pause
output [7:0] time_data// Remaining time
);
parameter s_idle=3'd0;
parameter s_start=3'd1;// Start
parameter s_suspend=3'd2;// Pause
parameter s_end=3'd3;// Stop
reg [2:0] state=s_idle;
reg [7:0] time_data_buf=8'd10;// Remaining time
always@(posedge clk_1Hz or negedge key_reset)
if(~key_reset)// Reset button, pressed high
state <= s_idle;
else
case(state)// Idle, set timing
s_idle:
if(key_start==0)// Start
state <= s_start;// Start
else
state <= s_idle;
s_start:
if(key_start==0)// Pause
state <= s_suspend;// Pause
else if(time_data_buf==8'd0)// Timing ends
state <= s_end;
else
state <= s_start;
s_suspend:
if(key_start==0)// Start
state <= s_start;// Start
else
state <= s_suspend;
s_end:
state <= s_end;
default:;
endcase
reg [7:0] D_count=8'd0;
always@(posedge clk_1Hz)
case(state)// Idle, set timing
s_idle:
// Display set time
if(key_add==0)// Add button, pressed high
time_data_buf <= time_data_buf+8'd1;
else if(key_sub==0)// Subtract button
if(time_data_buf==8'd0)
	time_data_buf <= 8'd0;
else
	time_data_buf <= time_data_buf-8'd1;
s_start:
if(time_data_buf==8'd0)
	time_data_buf <= 8'd0;
else
if(D_count==8'd59)
	time_data_buf <= time_data_buf-8'd1;// Countdown
s_end:
	time_data_buf <= 8'h0;// Display 0
default:;
endcase
always@(posedge clk_1Hz or negedge key_reset)
if(~key_reset)
D_count <= 8'd0;
else
if(state==s_start)
if(D_count==8'd59)
D_count <= 8'd0;
else
D_count <= D_count+8'd1;// Count 0~59
else
D_count <= D_count;
always@(*)
if(state==s_start)
if(D_count<8'd25)// 25s, 0~24
D1 <= 1;// Forward
else
D1 <= 0;
else
D1 <= 0;
always@(*)
if(state==s_start)
if((D_count>=8'd25 && D_count<=8'd29)||(D_count>=8'd55 && D_count<=8'd59))
D3 <= 1;// Pause
else
D3 <= 0;
else
D3 <= 0;
always@(*)
if(state==s_start)
if(D_count<=8'd54 && D_count>=8'd30)// 30~54
D2 <= 1;// Reverse
else
D2 <= 0;
else