The development of RISC-V is progressing well, but it seems to be following the path of ARM… … PreviouslyHennessy and Patterson proposed that RISC-V is a DSA, indicating that instructions should be modular (stability requires only the basic ISA to remain unchanged), and it should support high customization, serving as the foundation for custom accelerators to address the slowdown of Moore’s Law… … However, it seems that no one is paying attention to this; they only hear, “In 3 to 5 years, RISC-V will be everywhere.”
AI Workloads Need A New, Open Approach
Those who design CPUs and those who design GPGPUs are two different types of people… … they cannot fully understand each other. CPU designers are too accustomed to being at the center of the system, the C position, always hoping to plan for other components… … No, No, No, the obedient CPU designers will never understand the brutal demands of those working on AI… … The best approach is to focus solely on creating the basic IP, leaving ample room for accelerator engineers to innovate, including the instruction set, allowing them the freedom to create… … Then, after two years, standardize the common parts, rather than trying to establish a standard and hoping that everyone will develop based on that standard instruction set… … ARM follows a standard CPU development path, which is true, but it is only suitable for CPU development… … In the RISC-V camp, those who adhere to the CPU path can refer to the ARM route. However, if one seriously considers DSA, sufficient space must be left for Domain Specific Accelerators… …