Considerations for Connecting Dual Clock Domains in FPGA

Today, while studying the asynchronous FIFO read and write clock synchronization in FPGA, I noticed an issue: when connecting two different clocks, it is challenging to achieve complete synchronization. As a result, at a certain moment, the edge of the high-precision clock may appear in the middle of the edge of the low-precision clock, leading to the inability to meet Tsu and Thold. This is a point worth noting, as shown in the figure below:Considerations for Connecting Dual Clock Domains in FPGAIt can be seen that when the edge of CLK cannot meet Tsu or Tco, a metastable state will occur. The output of the flip-flop will remain in an uncertain state for a period of time, which is neither a high level “1” nor a low level “0”, or it may oscillate.Undoubtedly, if in communication, our master and slave devices mostly use different clocks, failing to minimize the impact of metastability can lead to communication errors or even crashes.Common methods include:Synchronizer method, oversampling, and replacing with higher precision devices.Here, I will introduce the synchronizer method:This is the most commonly used and fundamental method. The signal from the asynchronous domain (the sender) is passed through two (or more) cascaded flip-flops. The first flip-flop has a probability of entering a metastable state, but it is given a complete clock cycle to stabilize. The probability that the signal resampled by the second flip-flop is stable is greatly increased. The downside is that this method uses more resources.If two flip-flops are cascaded, the waveform is as follows:Considerations for Connecting Dual Clock Domains in FPGAAs shown in the figure, rx_reg0 is the first-level register in RX,and rx_reg0 is followed by another flip-flop. Therefore, when the oscillation time of the first-level register is long, the second-level register will capture the metastable state, but the signal output from the second-level register will be relatively stable.However, it is important to note: while this can capture a stable value, this stable value is independent of the input, making it impossible to determine the specific level state.It has been verified that the first-level register can achieve 70% stability, while the second level can reach 99%. Further improvements yield diminishing returns.

Related posts

  1. FPGA Tutorial Case 59: Deep Learning Case 6
  2. FPGA: The Next Generation Robot Perception Processor
  3. Why FPGA Technology is Becoming More Powerful: The Reasons Behind It
  4. Quick Start to Microcontroller Development: Mastering Soft Debugging Methods in Keil5
  5. Serving the Public: ‘Embedded’ Supervision Helps Migrant Workers Recover Unpaid Wages
  6. Xilinx 7 Series FPGA Pin Definition Design Guide
  7. Implementing LVDS High-Speed ADC Interface with Xilinx FPGA
  8. AI Machine Cerebellum – FPGA
  9. High-Performance Real-Time Signal Processing Platform Based on Virtex-7 FPGA
  10. Solutions for Industrial Automation Script Generation Based on Large Models in the Industrial Field
  11. Recommended Reading | Data Collection Planning for Enterprise Energy Management Systems
  12. STM32 Serial Bootloader Implementation
  13. Why the Robotics Sector Has Been Adjusting Recently
  14. Design of Image Acquisition Scheme for GigE Vision Camera Based on FPGA
  15. CPLD/FPGA Application Designer
  16. An OS-less Microcontroller Software Framework
  17. Comparison of PC Architecture vs Embedded Architecture for Recording Systems
  18. ECS-M.2/FPGA: PCI Express® EtherCAT® Slave Device Interface in M.2 Specification
  19. Energy Consumption Adaptive Wireless Sensor Network (WSN) Protocols: A Comparative Study of Leach, Leach-C, and Leach-E with Matlab Code

Leave a Comment