Xilinx released the groundbreaking Zynq® UltraScale+™ RFSoC (Radio Frequency System on Chip) first-generation product in February 2017, integrating high-performance RF data converters and RF-Analog technology on a single-chip SoC platform. It can integrate up to 16×16 RF sampling ADCs and DACs with programmable logic and an ARM multiprocessor subsystem, enabling flexible configuration and RF signal adjustment.
This February, the second and third generations of Zynq® UltraScale+™ RFSoC were released.The third generation will fully support direct RF sampling for frequency bands below 6GHz and expanded millimeter-wave interfaces, providing solutions for 5G wireless communication systems, advanced phased array radar, automotive radar, WeChat communication, and other applications.
Developing Large-Scale MIMO RF Cases
The left side of the figure shows the situation when using traditional SoCs, where the small black squares outside represent the ADCs and DACs. In addition to the 4 SoC chips, 32 converters are required to achieve 64×64 large-scale MIMO.
However, after using Xilinx’s Zynq UltraScale+ RFSoC, only 4 chips are needed to achieve the same 64×64 large-scale MIMO without additional converters. The number of chips is reduced from 36 to just 4, while power consumption is reduced by 50%, and board area is saved by 75%.
Large-Scale Multifunctional Phased Array Radar (MPAR) System
This is a product developed by Rockwell Collins, which combines four Zynq UltraScale+ RFSoC single-chip 16×16 transceiver modules to form a 64×64 transceiver panel, serving as a unified module for various MPAR systems to meet different applications.
Adaptive Direct RF Sampling Solution
In a superheterodyne structure, the receiver receives RF signals and downconverts them to a lower intermediate frequency (IF) before sampling and digitizing the signals. The RF front end must include bandpass filters, low-noise amplifiers, mixers, and local oscillators (LO).
A direct RF sampling receiver consists only of low-noise amplifiers, appropriate filters, and ADCs. The receiver does not require mixers and LOs; the ADC directly digitizes the RF signals and sends them to the processor for subsequent signal processing.
The Zynq UltraScale+ RFSoC uses a 16nm FinFET chip process, integrating RF-class analog components into a multiprocessor SoC (MPSoC), achieving a fully software and hardware programmable RF system on a single chip.
FPGA programmable logic perfectly combines with the ARM-class processing subsystem, using a 12-bit 4GSPS RF sampling ADC and a 14-bit 6.4GSPS direct RF DAC, while possessing optimal digital downconversion and upconversion signal processing capabilities.
The advantages of Zynq UltraScale+ RFSoC mainly lie in energy efficiency, reduced form factor, shortened design cycles, and design flexibility.
Today, send the keyword: 190228 to the WeChat public account “Radar Communication Electronic Warfare” to obtain the PDF reading version of the above text, as well as reference materials from Xilinx for a deeper understanding of the Zynq UltraScale+ RFSoC.
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