Hello everyone, I am Pi Zi Heng, a serious technical person. Today, I will share with you the three key factors affecting the speed limit of FlexSPI peripherals in i.MXRT.
FlexSPI is an essential peripheral when developing the i.MXRT series. Topics such as XIP performance, OTA design, and memory expansion all inevitably involve FlexSPI. Among these, the most concerning point is the speed limit of FlexSPI, which directly impacts the performance of the final application.
In the chip reference manual (RM), more emphasis is placed on the common functionalities of FlexSPI, while performance parameters like speed may vary by platform (there may be some differences between different chip models). Therefore, this differentiated information is often included in the chip data sheet (DS). Today, I will use the convoluted descriptions regarding FlexSPI speed in the RT1180 data sheet as an example to discuss the three key factors affecting the speed limit of FlexSPI:
1. Performance Design of FlexSPI Peripherals
From the first member of the i.MXRT family, the RT1050 (released in 2018), to the latest RT1180 (to be released in 2025), the functional design of the FlexSPI peripheral has undergone multiple iterations and optimizations, but it has consistently adhered to the same performance standard, which is to meet the 200MHz SDR/DDR timing (this refers only to the peripheral itself, but the final performance in the MCU system may suffer losses).
The performance limit of the FlexSPI peripheral itself can be considered a factor, but since this indicator is the same across the entire i.MXRT family, we will not specifically point out this influencing factor.
2. Clear RT3digits Data Sheet
When we open the RT500 DS (Rev.3) and find the FlexSPI Flash interface section, we can clearly see that the FlexSPI performance can reach its inherent limit, so there is no doubt here. (For a detailed explanation of the RX Clock source options, please refer to my previous article “Sampling Clock Sources for FlexSPI Peripherals in i.MXRT”).
It is necessary to point out the first factor affecting the performance limit of FlexSPI, which is the VDDCORE power supply voltage. As shown in the table below, the maximum clock frequency of FlexSPI varies at different voltage levels for the RT500:
Additionally, if some FlexSPI ports do not route the DQS signal from the PAD, the maximum performance cannot be achieved, such as with the RT600 PortB. Since this factor is a special case (for more details, see my previous article “FlexSPI Pin Groups in i.MXRT That Do Not Support DQS”), we will not specifically point it out here.
Unfortunately, the data sheet for the RT3digits series does not include an I/O AC parameter table (maximum frequency fmax, rise time tr, fall time tf, etc.), which may be because the RT3digits is derived from the LPC platform, and the LPC series data sheets also do not contain fmax. We will discuss the utility of fmax in the next section.
3. Three Influencing Factors Derived from the Confusing RT1180 Data Sheet
Before discussing the RT1180, let’s briefly review the data sheets for the RT10xx series, which are all single-core products with relatively simple MCU system architectures, so the FlexSPI performance descriptions are also quite clear. Although the limit does not reach SDR/DDR 200MHz, overclocking is not entirely impossible, as NXP chip designs generally leave a margin. Additionally, although the I/O AC parameter table does not include fmax, since the performance of each PAD group is consistent, we do not need to discuss this further for now.
Now let’s look at the dual-core products RT1170/1180, where the data sheet descriptions become a bit convoluted. From the RT1180 data sheet (Rev.7), we can see some interesting details. First, the PADs are classified into high-speed PADs with fmax 208MHz/200MHz and standard PADs with fmax 104MHz, which is the second factor affecting the speed limit of FlexSPI. If the PAD fmax performance is insufficient, the maximum frequency of FlexSPI will also be limited.
From the RT1180 data sheet, we see that the upper limit performance mentioned in the FlexSPI parameters section is still 166MHz SDR/DDR, which seems to be no different from the RT1050. But don’t worry, let’s continue to look:
If you look closely, you will find the supplementary tables for SDR200M and DDR200M, which indicate that the RT1180 actually supports 200MHz SDR/DDR, but only on FlexSPI1 (note that the RT1180 has two FlexSPI peripherals). This seems to be the third factor affecting the speed limit of FlexSPI (i.e., the number of FlexSPI peripherals). Different numbered FlexSPI peripherals may have different performance limits. This conclusion is both true and false; it is not that the performance of the FlexSPI peripherals themselves differs, but rather that the different numbered FlexSPI peripherals have different positions in the MCU system architecture, leading to performance differences (related to the path length between PADs). This is the true third influencing factor.
Therefore, the RT1180 data sheet includes the following summary, which comprehensively covers all influencing factors of FlexSPI performance. By now, you should no longer feel confused about the descriptions in the data sheet!
Thus, I have introduced the three key factors affecting the speed limit of FlexSPI peripherals in i.MXRT. Where’s the applause~~~